upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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263 lines
7.6 KiB
263 lines
7.6 KiB
# -*- coding: utf-8 -*-
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#
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# Copyright (c) 2011 The Chromium OS Authors.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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import os
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import tempfile
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import unittest
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import checkpatch
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import gitutil
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import patchstream
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import series
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class TestPatch(unittest.TestCase):
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"""Test this program
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TODO: Write tests for the rest of the functionality
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"""
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def testBasic(self):
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"""Test basic filter operation"""
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data='''
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From 656c9a8c31fa65859d924cd21da920d6ba537fad Mon Sep 17 00:00:00 2001
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From: Simon Glass <sjg@chromium.org>
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Date: Thu, 28 Apr 2011 09:58:51 -0700
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Subject: [PATCH (resend) 3/7] Tegra2: Add more clock support
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This adds functions to enable/disable clocks and reset to on-chip peripherals.
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cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type
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‘long long unsigned int’, but argument 3 has type
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‘u64 {aka long unsigned int}’ [-Wformat=]
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BUG=chromium-os:13875
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TEST=build U-Boot for Seaboard, boot
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Change-Id: I80fe1d0c0b7dd10aa58ce5bb1d9290b6664d5413
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Review URL: http://codereview.chromium.org/6900006
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Signed-off-by: Simon Glass <sjg@chromium.org>
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---
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arch/arm/cpu/armv7/tegra2/Makefile | 2 +-
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arch/arm/cpu/armv7/tegra2/ap20.c | 57 ++----
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arch/arm/cpu/armv7/tegra2/clock.c | 163 +++++++++++++++++
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'''
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expected='''
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From 656c9a8c31fa65859d924cd21da920d6ba537fad Mon Sep 17 00:00:00 2001
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From: Simon Glass <sjg@chromium.org>
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Date: Thu, 28 Apr 2011 09:58:51 -0700
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Subject: [PATCH (resend) 3/7] Tegra2: Add more clock support
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This adds functions to enable/disable clocks and reset to on-chip peripherals.
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cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type
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‘long long unsigned int’, but argument 3 has type
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‘u64 {aka long unsigned int}’ [-Wformat=]
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Signed-off-by: Simon Glass <sjg@chromium.org>
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---
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arch/arm/cpu/armv7/tegra2/Makefile | 2 +-
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arch/arm/cpu/armv7/tegra2/ap20.c | 57 ++----
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arch/arm/cpu/armv7/tegra2/clock.c | 163 +++++++++++++++++
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'''
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out = ''
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inhandle, inname = tempfile.mkstemp()
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infd = os.fdopen(inhandle, 'w')
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infd.write(data)
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infd.close()
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exphandle, expname = tempfile.mkstemp()
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expfd = os.fdopen(exphandle, 'w')
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expfd.write(expected)
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expfd.close()
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patchstream.FixPatch(None, inname, series.Series(), None)
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rc = os.system('diff -u %s %s' % (inname, expname))
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self.assertEqual(rc, 0)
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os.remove(inname)
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os.remove(expname)
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def GetData(self, data_type):
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data='''From 4924887af52713cabea78420eff03badea8f0035 Mon Sep 17 00:00:00 2001
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From: Simon Glass <sjg@chromium.org>
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Date: Thu, 7 Apr 2011 10:14:41 -0700
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Subject: [PATCH 1/4] Add microsecond boot time measurement
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This defines the basics of a new boot time measurement feature. This allows
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logging of very accurate time measurements as the boot proceeds, by using
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an available microsecond counter.
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%s
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---
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README | 11 ++++++++
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MAINTAINERS | 3 ++
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common/bootstage.c | 50 ++++++++++++++++++++++++++++++++++++
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include/bootstage.h | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++
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include/common.h | 8 ++++++
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5 files changed, 141 insertions(+), 0 deletions(-)
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create mode 100644 common/bootstage.c
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create mode 100644 include/bootstage.h
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diff --git a/README b/README
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index 6f3748d..f9e4e65 100644
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--- a/README
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+++ b/README
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@@ -2026,6 +2026,17 @@ The following options need to be configured:
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example, some LED's) on your board. At the moment,
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the following checkpoints are implemented:
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+- Time boot progress
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+ CONFIG_BOOTSTAGE
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+
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+ Define this option to enable microsecond boot stage timing
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+ on supported platforms. For this to work your platform
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+ needs to define a function timer_get_us() which returns the
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+ number of microseconds since reset. This would normally
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+ be done in your SOC or board timer.c file.
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+
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+ You can add calls to bootstage_mark() to set time markers.
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+
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- Standalone program support:
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CONFIG_STANDALONE_LOAD_ADDR
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diff --git a/MAINTAINERS b/MAINTAINERS
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index b167b028ec..beb7dc634f 100644
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -474,3 +474,8 @@ S: Maintained
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T: git git://git.denx.de/u-boot.git
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F: *
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F: */
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+
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+BOOTSTAGE
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+M: Simon Glass <sjg@chromium.org>
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+L: u-boot@lists.denx.de
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+F: common/bootstage.c
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diff --git a/common/bootstage.c b/common/bootstage.c
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new file mode 100644
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index 0000000..2234c87
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--- /dev/null
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+++ b/common/bootstage.c
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@@ -0,0 +1,37 @@
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+/*
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+ * Copyright (c) 2011, Google Inc. All rights reserved.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+/*
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+ * This module records the progress of boot and arbitrary commands, and
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+ * permits accurate timestamping of each. The records can optionally be
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+ * passed to kernel in the ATAGs
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+ */
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+
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+#include <common.h>
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+
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+struct bootstage_record {
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+ u32 time_us;
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+ const char *name;
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+};
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+
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+static struct bootstage_record record[BOOTSTAGE_COUNT];
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+
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+u32 bootstage_mark(enum bootstage_id id, const char *name)
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+{
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+ struct bootstage_record *rec = &record[id];
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+
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+ /* Only record the first event for each */
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+%sif (!rec->name) {
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+ rec->time_us = (u32)timer_get_us();
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+ rec->name = name;
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+ }
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+ if (!rec->name &&
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+ %ssomething_else) {
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+ rec->time_us = (u32)timer_get_us();
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+ rec->name = name;
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+ }
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+%sreturn rec->time_us;
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+}
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--
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1.7.3.1
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'''
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signoff = 'Signed-off-by: Simon Glass <sjg@chromium.org>\n'
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tab = ' '
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indent = ' '
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if data_type == 'good':
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pass
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elif data_type == 'no-signoff':
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signoff = ''
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elif data_type == 'spaces':
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tab = ' '
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elif data_type == 'indent':
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indent = tab
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else:
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print('not implemented')
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return data % (signoff, tab, indent, tab)
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def SetupData(self, data_type):
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inhandle, inname = tempfile.mkstemp()
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infd = os.fdopen(inhandle, 'w')
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data = self.GetData(data_type)
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infd.write(data)
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infd.close()
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return inname
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def testGood(self):
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"""Test checkpatch operation"""
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inf = self.SetupData('good')
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result = checkpatch.CheckPatch(inf)
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self.assertEqual(result.ok, True)
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self.assertEqual(result.problems, [])
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self.assertEqual(result.errors, 0)
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self.assertEqual(result.warnings, 0)
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self.assertEqual(result.checks, 0)
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self.assertEqual(result.lines, 62)
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os.remove(inf)
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def testNoSignoff(self):
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inf = self.SetupData('no-signoff')
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result = checkpatch.CheckPatch(inf)
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self.assertEqual(result.ok, False)
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self.assertEqual(len(result.problems), 1)
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self.assertEqual(result.errors, 1)
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self.assertEqual(result.warnings, 0)
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self.assertEqual(result.checks, 0)
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self.assertEqual(result.lines, 62)
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os.remove(inf)
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def testSpaces(self):
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inf = self.SetupData('spaces')
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result = checkpatch.CheckPatch(inf)
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self.assertEqual(result.ok, False)
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self.assertEqual(len(result.problems), 3)
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self.assertEqual(result.errors, 0)
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self.assertEqual(result.warnings, 3)
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self.assertEqual(result.checks, 0)
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self.assertEqual(result.lines, 62)
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os.remove(inf)
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def testIndent(self):
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inf = self.SetupData('indent')
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result = checkpatch.CheckPatch(inf)
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self.assertEqual(result.ok, False)
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self.assertEqual(len(result.problems), 1)
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self.assertEqual(result.errors, 0)
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self.assertEqual(result.warnings, 0)
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self.assertEqual(result.checks, 1)
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self.assertEqual(result.lines, 62)
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os.remove(inf)
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if __name__ == "__main__":
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unittest.main()
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gitutil.RunTests()
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