upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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663 lines
17 KiB
663 lines
17 KiB
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
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* has nothing to do with the flash chip being 8-bit or 16-bit.
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*/
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#ifdef CONFIG_FLASH_16BIT
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typedef unsigned short FLASH_PORT_WIDTH;
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typedef volatile unsigned short FLASH_PORT_WIDTHV;
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#define FLASH_ID_MASK 0xFFFF
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#else
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typedef unsigned long FLASH_PORT_WIDTH;
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typedef volatile unsigned long FLASH_PORT_WIDTHV;
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#define FLASH_ID_MASK 0xFFFFFFFF
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#endif
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define ORMASK(size) ((-size) & OR_AM_MSK)
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#define FLASH_CYCLE1 0x0555
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#define FLASH_CYCLE2 0x02aa
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size(FPWV *addr, flash_info_t *info);
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static void flash_reset(flash_info_t *info);
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static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
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static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
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static void flash_get_offsets(ulong base, flash_info_t *info);
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static flash_info_t *flash_get_info(ulong base);
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/*-----------------------------------------------------------------------
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* flash_init()
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*
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* sets up flash_info and returns size of FLASH (bytes)
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*/
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unsigned long flash_init (void)
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{
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unsigned long size = 0;
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int i;
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/* Init: no FLASHes known */
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for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
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#if 0
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ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
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#else
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ulong flashbase = CFG_FLASH_BASE;
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#endif
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memset(&flash_info[i], 0, sizeof(flash_info_t));
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flash_info[i].size =
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flash_get_size((FPW *)flashbase, &flash_info[i]);
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if (flash_info[i].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
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i, flash_info[i].size);
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}
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size += flash_info[i].size;
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}
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CFG_MONITOR_BASE,
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CFG_MONITOR_BASE+monitor_flash_len-1,
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flash_get_info(CFG_MONITOR_BASE));
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#endif
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#ifdef CFG_ENV_IS_IN_FLASH
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/* ENV protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR+CFG_ENV_SIZE-1,
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flash_get_info(CFG_ENV_ADDR));
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#endif
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return size ? size : 1;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_reset(flash_info_t *info)
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{
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FPWV *base = (FPWV *)(info->start[0]);
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/* Put FLASH back in read mode */
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
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*base = (FPW)0x00FF00FF; /* Intel Read Mode */
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else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
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*base = (FPW)0x00F000F0; /* AMD Read Mode */
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t *info)
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{
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int i;
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/* set up sector start address table */
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
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&& (info->flash_id & FLASH_BTYPE)) {
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int bootsect_size; /* number of bytes/boot sector */
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int sect_size; /* number of bytes/regular sector */
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bootsect_size = 0x00002000 * (sizeof(FPW)/2);
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sect_size = 0x00010000 * (sizeof(FPW)/2);
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/* set sector offsets for bottom boot block type */
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for (i = 0; i < 8; ++i) {
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info->start[i] = base + (i * bootsect_size);
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}
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for (i = 8; i < info->sector_count; i++) {
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info->start[i] = base + ((i - 7) * sect_size);
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}
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}
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else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
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&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
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int sect_size; /* number of bytes/sector */
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sect_size = 0x00010000 * (sizeof(FPW)/2);
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/* set up sector start address table (uniform sector type) */
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for( i = 0; i < info->sector_count; i++ )
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info->start[i] = base + (i * sect_size);
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}
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}
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/*-----------------------------------------------------------------------
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*/
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static flash_info_t *flash_get_info(ulong base)
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{
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int i;
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flash_info_t * info;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
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info = & flash_info[i];
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if (info->start[0] <= base && base < info->start[0] + info->size)
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break;
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}
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return i == CFG_MAX_FLASH_BANKS ? 0 : info;
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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uchar *boottype;
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uchar *bootletter;
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uchar *fmt;
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uchar botbootletter[] = "B";
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uchar topbootletter[] = "T";
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uchar botboottype[] = "bottom boot sector";
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uchar topboottype[] = "top boot sector";
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
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case FLASH_MAN_SST: printf ("SST "); break;
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case FLASH_MAN_STM: printf ("STM "); break;
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case FLASH_MAN_INTEL: printf ("INTEL "); break;
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default: printf ("Unknown Vendor "); break;
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}
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/* check for top or bottom boot, if it applies */
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if (info->flash_id & FLASH_BTYPE) {
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boottype = botboottype;
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bootletter = botbootletter;
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}
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else {
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boottype = topboottype;
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bootletter = topbootletter;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM640U:
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fmt = "29LV641D (64 Mbit, uniform sectors)\n";
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break;
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case FLASH_28F800C3B:
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case FLASH_28F800C3T:
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fmt = "28F800C3%s (8 Mbit, %s)\n";
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break;
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case FLASH_INTEL800B:
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case FLASH_INTEL800T:
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fmt = "28F800B3%s (8 Mbit, %s)\n";
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break;
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case FLASH_28F160C3B:
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case FLASH_28F160C3T:
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fmt = "28F160C3%s (16 Mbit, %s)\n";
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break;
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case FLASH_INTEL160B:
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case FLASH_INTEL160T:
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fmt = "28F160B3%s (16 Mbit, %s)\n";
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break;
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case FLASH_28F320C3B:
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case FLASH_28F320C3T:
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fmt = "28F320C3%s (32 Mbit, %s)\n";
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break;
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case FLASH_INTEL320B:
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case FLASH_INTEL320T:
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fmt = "28F320B3%s (32 Mbit, %s)\n";
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break;
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case FLASH_28F640C3B:
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case FLASH_28F640C3T:
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fmt = "28F640C3%s (64 Mbit, %s)\n";
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break;
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case FLASH_INTEL640B:
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case FLASH_INTEL640T:
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fmt = "28F640B3%s (64 Mbit, %s)\n";
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break;
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default:
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fmt = "Unknown Chip Type\n";
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break;
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}
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printf (fmt, bootletter, boottype);
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20,
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info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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if ((i % 5) == 0) {
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printf ("\n ");
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}
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printf (" %08lX%s", info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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}
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/*-----------------------------------------------------------------------
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*/
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/*
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* The following code cannot be run from FLASH!
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*/
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ulong flash_get_size (FPWV *addr, flash_info_t *info)
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{
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/* Write auto select command: read Manufacturer ID */
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/* Write auto select command sequence and test FLASH answer */
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addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
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addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
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addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
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/* The manufacturer codes are only 1 byte, so just use 1 byte.
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* This works for any bus width and any FLASH device width.
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*/
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udelay(100);
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switch (addr[0] & 0xff) {
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case (uchar)AMD_MANUFACT:
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info->flash_id = FLASH_MAN_AMD;
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break;
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case (uchar)INTEL_MANUFACT:
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info->flash_id = FLASH_MAN_INTEL;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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break;
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}
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/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
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if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
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case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
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info->flash_id += FLASH_AM640U;
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info->sector_count = 128;
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info->size = 0x00800000 * (sizeof(FPW)/2);
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break; /* => 8 or 16 MB */
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case (FPW)INTEL_ID_28F800C3B:
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info->flash_id += FLASH_28F800C3B;
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info->sector_count = 23;
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info->size = 0x00100000 * (sizeof(FPW)/2);
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break; /* => 1 or 2 MB */
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case (FPW)INTEL_ID_28F800B3B:
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info->flash_id += FLASH_INTEL800B;
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info->sector_count = 23;
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info->size = 0x00100000 * (sizeof(FPW)/2);
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break; /* => 1 or 2 MB */
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case (FPW)INTEL_ID_28F160C3B:
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info->flash_id += FLASH_28F160C3B;
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info->sector_count = 39;
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info->size = 0x00200000 * (sizeof(FPW)/2);
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break; /* => 2 or 4 MB */
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case (FPW)INTEL_ID_28F160B3B:
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info->flash_id += FLASH_INTEL160B;
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info->sector_count = 39;
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info->size = 0x00200000 * (sizeof(FPW)/2);
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break; /* => 2 or 4 MB */
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case (FPW)INTEL_ID_28F320C3B:
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info->flash_id += FLASH_28F320C3B;
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info->sector_count = 71;
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info->size = 0x00400000 * (sizeof(FPW)/2);
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break; /* => 4 or 8 MB */
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case (FPW)INTEL_ID_28F320B3B:
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info->flash_id += FLASH_INTEL320B;
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info->sector_count = 71;
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info->size = 0x00400000 * (sizeof(FPW)/2);
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break; /* => 4 or 8 MB */
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case (FPW)INTEL_ID_28F640C3B:
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info->flash_id += FLASH_28F640C3B;
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info->sector_count = 135;
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info->size = 0x00800000 * (sizeof(FPW)/2);
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break; /* => 8 or 16 MB */
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case (FPW)INTEL_ID_28F640B3B:
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info->flash_id += FLASH_INTEL640B;
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info->sector_count = 135;
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info->size = 0x00800000 * (sizeof(FPW)/2);
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break; /* => 8 or 16 MB */
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0); /* => no or unknown flash */
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}
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flash_get_offsets((ulong)addr, info);
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/* Put FLASH back in read mode */
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flash_reset(info);
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return (info->size);
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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FPWV *addr;
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int flag, prot, sect;
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int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
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ulong start, now, last;
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int rcode = 0;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
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printf ("- no sectors to erase\n");
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}
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return 1;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_INTEL800B:
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case FLASH_INTEL160B:
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case FLASH_INTEL320B:
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case FLASH_INTEL640B:
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case FLASH_28F800C3B:
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case FLASH_28F160C3B:
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case FLASH_28F320C3B:
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case FLASH_28F640C3B:
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case FLASH_AM640U:
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break;
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case FLASH_UNKNOWN:
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default:
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printf ("Can't erase unknown flash type %08lx - aborted\n",
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info->flash_id);
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return 1;
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}
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prot = 0;
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for (sect=s_first; sect<=s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf ("\n");
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}
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last = get_timer(0);
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
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if (info->protect[sect] != 0) /* protected, skip it */
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continue;
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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addr = (FPWV *)(info->start[sect]);
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if (intel) {
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*addr = (FPW)0x00500050; /* clear status register */
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*addr = (FPW)0x00200020; /* erase setup */
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*addr = (FPW)0x00D000D0; /* erase confirm */
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}
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else {
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/* must be AMD style if not Intel */
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FPWV *base; /* first address in bank */
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base = (FPWV *)(info->start[0]);
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base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
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base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
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base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
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base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
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base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
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*addr = (FPW)0x00300030; /* erase sector */
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}
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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start = get_timer(0);
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/* wait at least 50us for AMD, 80us for Intel.
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* Let's wait 1 ms.
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*/
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udelay (1000);
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while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
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if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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if (intel) {
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/* suspend erase */
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*addr = (FPW)0x00B000B0;
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}
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flash_reset(info); /* reset to read mode */
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rcode = 1; /* failed */
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break;
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}
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/* show that we're waiting */
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if ((get_timer(last)) > CFG_HZ) {/* every second */
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putc ('.');
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last = get_timer(0);
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}
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}
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/* show that we're waiting */
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if ((get_timer(last)) > CFG_HZ) { /* every second */
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putc ('.');
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last = get_timer(0);
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}
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|
|
flash_reset(info); /* reset to read mode */
|
|
}
|
|
|
|
printf (" done\n");
|
|
return rcode;
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Copy memory to flash, returns:
|
|
* 0 - OK
|
|
* 1 - write timeout
|
|
* 2 - Flash not erased
|
|
*/
|
|
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
|
{
|
|
FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
|
|
int bytes; /* number of bytes to program in current word */
|
|
int left; /* number of bytes left to program */
|
|
int i, res;
|
|
|
|
for (left = cnt, res = 0;
|
|
left > 0 && res == 0;
|
|
addr += sizeof(data), left -= sizeof(data) - bytes) {
|
|
|
|
bytes = addr & (sizeof(data) - 1);
|
|
addr &= ~(sizeof(data) - 1);
|
|
|
|
/* combine source and destination data so can program
|
|
* an entire word of 16 or 32 bits
|
|
*/
|
|
for (i = 0; i < sizeof(data); i++) {
|
|
data <<= 8;
|
|
if (i < bytes || i - bytes >= left )
|
|
data += *((uchar *)addr + i);
|
|
else
|
|
data += *src++;
|
|
}
|
|
|
|
/* write one word to the flash */
|
|
switch (info->flash_id & FLASH_VENDMASK) {
|
|
case FLASH_MAN_AMD:
|
|
res = write_word_amd(info, (FPWV *)addr, data);
|
|
break;
|
|
case FLASH_MAN_INTEL:
|
|
res = write_word_intel(info, (FPWV *)addr, data);
|
|
break;
|
|
default:
|
|
/* unknown flash type, error! */
|
|
printf ("missing or unknown FLASH type\n");
|
|
res = 1; /* not really a timeout, but gives error */
|
|
break;
|
|
}
|
|
}
|
|
|
|
return (res);
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Write a word to Flash for AMD FLASH
|
|
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
|
* (not an individual chip) is.
|
|
*
|
|
* returns:
|
|
* 0 - OK
|
|
* 1 - write timeout
|
|
* 2 - Flash not erased
|
|
*/
|
|
static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
|
|
{
|
|
ulong start;
|
|
int flag;
|
|
int res = 0; /* result, assume success */
|
|
FPWV *base; /* first address in flash bank */
|
|
|
|
/* Check if Flash is (sufficiently) erased */
|
|
if ((*dest & data) != data) {
|
|
return (2);
|
|
}
|
|
|
|
|
|
base = (FPWV *)(info->start[0]);
|
|
|
|
/* Disable interrupts which might cause a timeout here */
|
|
flag = disable_interrupts();
|
|
|
|
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
|
|
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
|
|
base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
|
|
|
|
*dest = data; /* start programming the data */
|
|
|
|
/* re-enable interrupts if necessary */
|
|
if (flag)
|
|
enable_interrupts();
|
|
|
|
start = get_timer (0);
|
|
|
|
/* data polling for D7 */
|
|
while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
|
|
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
|
*dest = (FPW)0x00F000F0; /* reset bank */
|
|
res = 1;
|
|
}
|
|
}
|
|
|
|
return (res);
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Write a word to Flash for Intel FLASH
|
|
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
|
* (not an individual chip) is.
|
|
*
|
|
* returns:
|
|
* 0 - OK
|
|
* 1 - write timeout
|
|
* 2 - Flash not erased
|
|
*/
|
|
static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
|
|
{
|
|
ulong start;
|
|
int flag;
|
|
int res = 0; /* result, assume success */
|
|
|
|
/* Check if Flash is (sufficiently) erased */
|
|
if ((*dest & data) != data) {
|
|
return (2);
|
|
}
|
|
|
|
/* Disable interrupts which might cause a timeout here */
|
|
flag = disable_interrupts();
|
|
|
|
*dest = (FPW)0x00500050; /* clear status register */
|
|
*dest = (FPW)0x00FF00FF; /* make sure in read mode */
|
|
*dest = (FPW)0x00400040; /* program setup */
|
|
|
|
*dest = data; /* start programming the data */
|
|
|
|
/* re-enable interrupts if necessary */
|
|
if (flag)
|
|
enable_interrupts();
|
|
|
|
start = get_timer (0);
|
|
|
|
while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
|
|
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
|
*dest = (FPW)0x00B000B0; /* Suspend program */
|
|
res = 1;
|
|
}
|
|
}
|
|
|
|
if (res == 0 && (*dest & (FPW)0x00100010))
|
|
res = 1; /* write failed, time out error is close enough */
|
|
|
|
*dest = (FPW)0x00500050; /* clear status register */
|
|
*dest = (FPW)0x00FF00FF; /* make sure in read mode */
|
|
|
|
return (res);
|
|
}
|
|
|