upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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302 lines
9.3 KiB
302 lines
9.3 KiB
/*
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* (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
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*
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* (C) Copyright 2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx5x_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/errno.h>
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#include <netdev.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <asm/gpio.h>
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/* NOR flash configuration */
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#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2))
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#define IMA3_MX53_CS0GCR2 0
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#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15))
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#define IMA3_MX53_CS0RCR2 0
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#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15))
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#define IMA3_MX53_CS0WCR2 0
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DECLARE_GLOBAL_DATA_PTR;
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static void weim_nor_settings(void)
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{
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struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
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writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1);
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writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2);
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writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1);
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writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2);
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writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1);
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writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2);
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writel(0x0, &weim_regs->wcr);
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set_chipselect_size(CS0_128);
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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/* UART4 RXD */
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mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D13,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
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PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
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mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
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/* UART4 TXD */
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mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D12,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
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PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
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}
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static void setup_iomux_fec(void)
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{
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/*FEC_MDIO*/
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mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
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/*FEC_MDC*/
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mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
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/* FEC RXD3 */
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mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC RXD2 */
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mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC RXD1 */
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mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC RXD0 */
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mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC TXD3 */
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mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH);
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/* FEC TXD2 */
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mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH);
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/* FEC TXD1 */
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mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
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/* FEC TXD0 */
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mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
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/* FEC TX_EN */
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mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
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/* FEC TX_CLK */
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mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC RX_ER */
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mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC RX_DV */
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mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC CRS */
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mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC COL */
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mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0);
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/* FEC RX_CLK */
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mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0);
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR };
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int board_mmc_getcd(struct mmc *mmc)
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{
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int ret;
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ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX53_PIN_GPIO_1,
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PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
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PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
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PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE);
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gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
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mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
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PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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return fsl_esdhc_initialize(bis, &esdhc_cfg);
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}
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#endif
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static void setup_iomux_spi(void)
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{
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/* SCLK */
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mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1);
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/* MOSI */
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mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1);
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/* MISO */
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mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1);
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/* SSEL 0 */
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mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1);
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}
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int board_early_init_f(void)
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{
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/* configure I/O pads */
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setup_iomux_uart();
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setup_iomux_fec();
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weim_nor_settings();
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/* configure spi */
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setup_iomux_spi();
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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mxc_set_sata_internal_clock();
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return 0;
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}
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#if defined(CONFIG_RESET_PHY_R)
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#include <miiphy.h>
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void reset_phy(void)
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{
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unsigned short reg;
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/* reset the phy */
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miiphy_reset("FEC", CONFIG_PHY_ADDR);
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/* set hard link to 100Mbit, full-duplex */
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miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, ®);
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reg &= ~BMCR_ANENABLE;
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reg |= (BMCR_SPEED100 | BMCR_FULLDPLX);
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miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg);
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miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®);
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reg |= (1 << 5);
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miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg);
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}
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#endif
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int checkboard(void)
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{
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puts("Board: IMA3_MX53\n");
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return 0;
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}
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