upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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463 lines
9.8 KiB
463 lines
9.8 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Board functions for TI AM335X based pxm2 board
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* (C) Copyright 2013 Siemens Schweiz AG
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* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* u-boot:/board/ti/am335x/board.c
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*
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* Board functions for TI AM335X based boards
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#include <common.h>
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#include <environment.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include "../../../drivers/video/da8xx-fb.h"
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <watchdog.h>
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#include "board.h"
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#include "../common/factoryset.h"
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#include "pmic.h"
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#include <nand.h>
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#include <bmp_layout.h>
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#ifdef CONFIG_SPL_BUILD
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static void board_init_ddr(void)
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{
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struct emif_regs pxm2_ddr3_emif_reg_data = {
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.sdram_config = 0x41805332,
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.sdram_tim1 = 0x666b3c9,
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.sdram_tim2 = 0x243631ca,
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.sdram_tim3 = 0x33f,
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.emif_ddr_phy_ctlr_1 = 0x100005,
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.zq_config = 0,
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.ref_ctrl = 0x81a,
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};
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struct ddr_data pxm2_ddr3_data = {
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.datardsratio0 = 0x81204812,
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.datawdsratio0 = 0,
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.datafwsratio0 = 0x8020080,
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.datawrsratio0 = 0x4010040,
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};
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struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
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.cmd0csratio = 0x80,
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.cmd0iclkout = 0,
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.cmd1csratio = 0x80,
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.cmd1iclkout = 0,
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.cmd2csratio = 0x80,
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.cmd2iclkout = 0,
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};
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const struct ctrl_ioregs ioregs = {
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.cm0ioctl = DDR_IOCTRL_VAL,
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.cm1ioctl = DDR_IOCTRL_VAL,
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.cm2ioctl = DDR_IOCTRL_VAL,
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.dt0ioctl = DDR_IOCTRL_VAL,
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.dt1ioctl = DDR_IOCTRL_VAL,
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};
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config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
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&pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
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}
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/*
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* voltage switching for MPU frequency switching.
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* @module = mpu - 0, core - 1
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* @vddx_op_vol_sel = vdd voltage to set
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*/
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#define MPU 0
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#define CORE 1
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int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
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{
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uchar buf[4];
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unsigned int reg_offset;
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if (module == MPU)
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reg_offset = PMIC_VDD1_OP_REG;
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else
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reg_offset = PMIC_VDD2_OP_REG;
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/* Select VDDx OP */
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if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
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return 1;
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buf[0] &= ~PMIC_OP_REG_CMD_MASK;
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if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
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return 1;
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/* Configure VDDx OP Voltage */
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if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
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return 1;
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buf[0] &= ~PMIC_OP_REG_SEL_MASK;
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buf[0] |= vddx_op_vol_sel;
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if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
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return 1;
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if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
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return 1;
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if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
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return 1;
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return 0;
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}
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#define OSC (V_OSCK/1000000)
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const struct dpll_params dpll_mpu_pxm2 = {
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720, OSC-1, 1, -1, -1, -1, -1};
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void spl_siemens_board_init(void)
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{
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uchar buf[4];
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/*
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* pxm2 PMIC code. All boards currently want an MPU voltage
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* of 1.2625V and CORE voltage of 1.1375V to operate at
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* 720MHz.
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*/
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if (i2c_probe(PMIC_CTRL_I2C_ADDR))
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return;
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/* VDD1/2 voltage selection register access by control i/f */
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if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
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return;
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buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
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if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
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return;
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/* Frequency switching for OPP 120 */
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if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
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voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
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printf("voltage update failed\n");
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}
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}
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#endif /* if def CONFIG_SPL_BUILD */
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int read_eeprom(void)
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{
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/* nothing ToDo here for this board */
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return 0;
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}
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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.phy_if = PHY_INTERFACE_MODE_RMII,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_addr = 1,
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.phy_if = PHY_INTERFACE_MODE_RMII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 4,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
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#if defined(CONFIG_DRIVER_TI_CPSW) || \
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(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
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int board_eth_init(bd_t *bis)
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{
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int n = 0;
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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#ifdef CONFIG_FACTORYSET
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int rv;
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if (!is_valid_ethaddr(factory_dat.mac))
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printf("Error: no valid mac address\n");
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else
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eth_env_set_enetaddr("ethaddr", factory_dat.mac);
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#endif /* #ifdef CONFIG_FACTORYSET */
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/* Set rgmii mode and enable rmii clock to be sourced from chip */
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writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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#endif
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return n;
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}
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#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
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#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
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static struct da8xx_panel lcd_panels[] = {
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/* AUO G156XW01 V1 */
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[0] = {
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.name = "AUO_G156XW01_V1",
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.width = 1376,
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.height = 768,
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.hfp = 14,
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.hbp = 64,
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.hsw = 56,
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.vfp = 1,
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.vbp = 28,
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.vsw = 3,
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.pxl_clk = 60000000,
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.invert_pxl_clk = 0,
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},
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/* AUO B101EVN06 V0 */
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[1] = {
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.name = "AUO_B101EVN06_V0",
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.width = 1280,
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.height = 800,
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.hfp = 52,
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.hbp = 84,
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.hsw = 36,
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.vfp = 3,
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.vbp = 14,
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.vsw = 6,
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.pxl_clk = 60000000,
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.invert_pxl_clk = 0,
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},
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/*
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* Settings from factoryset
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* stored in EEPROM
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*/
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[2] = {
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.name = "factoryset",
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.width = 0,
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.height = 0,
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.hfp = 0,
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.hbp = 0,
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.hsw = 0,
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.vfp = 0,
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.vbp = 0,
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.vsw = 0,
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.pxl_clk = 60000000,
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.invert_pxl_clk = 0,
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},
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};
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static const struct display_panel disp_panel = {
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WVGA,
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32,
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16,
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COLOR_ACTIVE,
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};
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static const struct lcd_ctrl_config lcd_cfg = {
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&disp_panel,
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.ac_bias = 255,
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.ac_bias_intrpt = 0,
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.dma_burst_sz = 16,
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.bpp = 32,
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.fdd = 0x80,
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.tft_alt_mode = 0,
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.stn_565_mode = 0,
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.mono_8bit_mode = 0,
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.invert_line_clock = 1,
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.invert_frm_clock = 1,
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.sync_edge = 0,
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.sync_ctrl = 1,
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.raster_order = 0,
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};
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static int set_gpio(int gpio, int state)
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{
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gpio_request(gpio, "temp");
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gpio_direction_output(gpio, state);
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gpio_set_value(gpio, state);
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gpio_free(gpio);
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return 0;
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}
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static int enable_backlight(void)
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{
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set_gpio(BOARD_LCD_POWER, 1);
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set_gpio(BOARD_BACK_LIGHT, 1);
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set_gpio(BOARD_TOUCH_POWER, 1);
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return 0;
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}
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static int enable_pwm(void)
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{
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struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
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struct pwmss_ecap_regs *ecap;
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int ticks = PWM_TICKS;
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int duty = PWM_DUTY;
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ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
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/* enable clock */
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setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
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/* TimeStam Counter register */
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writel(0xdb9, &ecap->tsctr);
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/* config period */
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writel(ticks - 1, &ecap->cap3);
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writel(ticks - 1, &ecap->cap1);
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setbits_le16(&ecap->ecctl2,
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(ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
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/* config duty */
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writel(duty, &ecap->cap2);
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writel(duty, &ecap->cap4);
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/* start */
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setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
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return 0;
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}
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static struct dpll_regs dpll_lcd_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x98,
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.cm_idlest_dpll = CM_WKUP + 0x48,
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.cm_clksel_dpll = CM_WKUP + 0x54,
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};
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/* no console on this board */
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int board_cfb_skip(void)
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{
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return 1;
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}
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#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
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#define PLL_GET_N(v) (v & 0x7f)
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static int get_clk(struct dpll_regs *dpll_regs)
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{
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unsigned int val;
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unsigned int m, n;
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int f = 0;
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val = readl(dpll_regs->cm_clksel_dpll);
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m = PLL_GET_M(val);
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n = PLL_GET_N(val);
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f = (m * V_OSCK) / n;
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return f;
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};
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int clk_get(int clk)
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{
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return get_clk(&dpll_lcd_regs);
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};
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static int conf_disp_pll(int m, int n)
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{
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struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
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struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
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struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
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u32 *const clk_domains[] = {
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&cmper->lcdclkctrl,
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0
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};
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u32 *const clk_modules_explicit_en[] = {
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&cmper->lcdclkctrl,
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&cmper->lcdcclkstctrl,
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&cmper->epwmss0clkctrl,
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0
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};
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do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
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writel(0x0, &cmdpll->clklcdcpixelclk);
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do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
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return 0;
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}
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static int board_video_init(void)
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{
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conf_disp_pll(24, 1);
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if (factory_dat.pxm50)
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da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
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else
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da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
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enable_pwm();
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enable_backlight();
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return 0;
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}
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#endif
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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int ret;
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omap_nand_switch_ecc(1, 8);
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#ifdef CONFIG_FACTORYSET
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if (factory_dat.asn[0] != 0) {
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char tmp[2 * MAX_STRING_LENGTH + 2];
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if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
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factory_dat.pxm50 = 1;
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else
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factory_dat.pxm50 = 0;
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sprintf(tmp, "%s_%s", factory_dat.asn,
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factory_dat.comp_version);
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ret = env_set("boardid", tmp);
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if (ret)
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printf("error setting board id\n");
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} else {
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factory_dat.pxm50 = 1;
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ret = env_set("boardid", "PXM50_1.0");
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if (ret)
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printf("error setting board id\n");
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}
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debug("PXM50: %d\n", factory_dat.pxm50);
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#endif
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return 0;
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}
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#endif
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#include "../common/board.c"
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