upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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239 lines
3.3 KiB
239 lines
3.3 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Clock specification for Xilinx ZynqMP
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*
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* (C) Copyright 2015 - 2018, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/ {
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clk100: clk100 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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u-boot,dm-pre-reloc;
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};
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clk125: clk125 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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clk200: clk200 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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u-boot,dm-pre-reloc;
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};
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clk250: clk250 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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clk300: clk300 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <300000000>;
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};
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clk600: clk600 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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};
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dp_aclk: clock0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-accuracy = <100>;
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};
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dp_aud_clk: clock1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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clock-accuracy = <100>;
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};
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dpdma_clk: dpdma_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <533000000>;
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};
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drm_clock: drm_clock {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <262750000>;
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clock-accuracy = <0x64>;
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};
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};
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&can0 {
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clocks = <&clk100 &clk100>;
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};
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&can1 {
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clocks = <&clk100 &clk100>;
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};
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&fpd_dma_chan1 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan2 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan3 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan4 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan5 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan6 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan7 {
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clocks = <&clk600>, <&clk100>;
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};
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&fpd_dma_chan8 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan1 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan2 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan3 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan4 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan5 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan6 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan7 {
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clocks = <&clk600>, <&clk100>;
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};
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&lpd_dma_chan8 {
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clocks = <&clk600>, <&clk100>;
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};
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&nand0 {
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clocks = <&clk100 &clk100>;
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};
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&gem0 {
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clocks = <&clk125>, <&clk125>, <&clk125>;
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};
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&gem1 {
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clocks = <&clk125>, <&clk125>, <&clk125>;
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};
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&gem2 {
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clocks = <&clk125>, <&clk125>, <&clk125>;
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};
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&gem3 {
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clocks = <&clk125>, <&clk125>, <&clk125>;
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};
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&gpio {
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clocks = <&clk100>;
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};
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&i2c0 {
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clocks = <&clk100>;
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};
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&i2c1 {
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clocks = <&clk100>;
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};
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&qspi {
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clocks = <&clk300 &clk300>;
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};
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&sata {
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clocks = <&clk250>;
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};
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&sdhci0 {
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clocks = <&clk200 &clk200>;
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};
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&sdhci1 {
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clocks = <&clk200 &clk200>;
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};
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&spi0 {
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clocks = <&clk200 &clk200>;
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};
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&spi1 {
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clocks = <&clk200 &clk200>;
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};
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&uart0 {
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clocks = <&clk100 &clk100>;
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};
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&uart1 {
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clocks = <&clk100 &clk100>;
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};
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&usb0 {
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clocks = <&clk250>, <&clk250>;
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};
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&usb1 {
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clocks = <&clk250>, <&clk250>;
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};
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&watchdog0 {
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clocks = <&clk100>;
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};
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&xilinx_drm {
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clocks = <&drm_clock>;
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};
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&xlnx_dp {
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clocks = <&dp_aclk>, <&dp_aud_clk>;
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};
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&xlnx_dpdma {
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clocks = <&dpdma_clk>;
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};
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&xlnx_dp_snd_codec0 {
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clocks = <&dp_aud_clk>;
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};
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