upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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49 lines
2.0 KiB
49 lines
2.0 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _TEGRA20_GP_PADCTRL_H_
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#define _TEGRA20_GP_PADCTRL_H_
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#include <asm/arch-tegra/gp_padctrl.h>
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/* APB_MISC_GP and padctrl registers */
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struct apb_misc_gp_ctlr {
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u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
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u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
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u32 reserved0[22]; /* 0x08 - 0x5C: */
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u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
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u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
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u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
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u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
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u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
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u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
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u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */
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u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */
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u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */
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u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */
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u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */
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u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */
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u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */
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u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */
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u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */
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u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */
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u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */
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u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */
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u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */
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u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */
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u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */
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u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */
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u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */
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u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */
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u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */
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u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */
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u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */
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u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */
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u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */
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u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
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};
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#endif /* _TEGRA20_GP_PADCTRL_H_ */
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