upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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388 lines
12 KiB
388 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <errno.h>
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#include <div64.h>
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#include <asm/io.h>
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#include <wait_bit.h>
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#include <asm/arch/firewall_s10.h>
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#include <asm/arch/sdram_s10.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/reset_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_system_manager *sysmgr_regs =
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(void *)SOCFPGA_SYSMGR_ADDRESS;
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#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
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/* The followring are the supported configurations */
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u32 ddr_config[] = {
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/* DDR_CONFIG(Address order,Bank,Column,Row) */
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/* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
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DDR_CONFIG(0, 3, 10, 12),
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DDR_CONFIG(0, 3, 9, 13),
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DDR_CONFIG(0, 3, 10, 13),
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DDR_CONFIG(0, 3, 9, 14),
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DDR_CONFIG(0, 3, 10, 14),
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DDR_CONFIG(0, 3, 10, 15),
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DDR_CONFIG(0, 3, 11, 14),
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DDR_CONFIG(0, 3, 11, 15),
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DDR_CONFIG(0, 3, 10, 16),
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DDR_CONFIG(0, 3, 11, 16),
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DDR_CONFIG(0, 3, 12, 15), /* 0xa */
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/* List for DDR4 only (pinout order > chip, bank, row, column) */
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DDR_CONFIG(1, 3, 10, 14),
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DDR_CONFIG(1, 4, 10, 14),
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DDR_CONFIG(1, 3, 10, 15),
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DDR_CONFIG(1, 4, 10, 15),
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DDR_CONFIG(1, 3, 10, 16),
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DDR_CONFIG(1, 4, 10, 16),
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DDR_CONFIG(1, 3, 10, 17),
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DDR_CONFIG(1, 4, 10, 17),
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};
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static u32 hmc_readl(u32 reg)
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{
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return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO48_ADDRESS + (reg)));
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}
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static u32 hmc_ecc_readl(u32 reg)
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{
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return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
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}
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static u32 hmc_ecc_writel(u32 data, u32 reg)
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{
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return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
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}
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static u32 ddr_sch_writel(u32 data, u32 reg)
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{
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return writel(data,
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(void __iomem *)SOCFPGA_SDR_SCHEDULER_ADDRESS + (reg));
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}
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int match_ddr_conf(u32 ddr_conf)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
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if (ddr_conf == ddr_config[i])
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return i;
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}
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return 0;
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}
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static int emif_clear(void)
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{
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hmc_ecc_writel(0, RSTHANDSHAKECTRL);
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return wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
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RSTHANDSHAKESTAT),
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DDR_HMC_RSTHANDSHAKE_MASK,
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false, 1000, false);
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}
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static int emif_reset(void)
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{
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u32 c2s, s2c, ret;
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c2s = hmc_ecc_readl(RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
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s2c = hmc_ecc_readl(RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
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debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
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c2s, s2c, hmc_readl(NIOSRESERVED0), hmc_readl(NIOSRESERVED1),
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hmc_readl(NIOSRESERVED2), hmc_readl(DRAMSTS));
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if (s2c && emif_clear()) {
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printf("DDR: emif_clear() failed\n");
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return -1;
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}
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debug("DDR: Triggerring emif reset\n");
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hmc_ecc_writel(DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
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/* if seq2core[3] = 0, we are good */
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ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
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RSTHANDSHAKESTAT),
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DDR_HMC_SEQ2CORE_INT_RESP_MASK,
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false, 1000, false);
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if (ret) {
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printf("DDR: failed to get ack from EMIF\n");
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return ret;
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}
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ret = emif_clear();
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if (ret) {
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printf("DDR: emif_clear() failed\n");
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return ret;
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}
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debug("DDR: %s triggered successly\n", __func__);
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return 0;
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}
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static int poll_hmc_clock_status(void)
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{
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return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
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SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
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}
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/**
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* sdram_mmr_init_full() - Function to initialize SDRAM MMR
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*
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* Initialize the SDRAM MMR.
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*/
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int sdram_mmr_init_full(unsigned int unused)
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{
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u32 update_value, io48_value, ddrioctl;
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u32 i;
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int ret;
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/* Enable access to DDR from CPU master */
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clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
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CCU_ADBASE_DI_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
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CCU_ADBASE_DI_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
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CCU_ADBASE_DI_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
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CCU_ADBASE_DI_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
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CCU_ADBASE_DI_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
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CCU_ADBASE_DI_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
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CCU_ADBASE_DI_MASK);
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/* Enable access to DDR from IO master */
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clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
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CCU_ADBASE_DI_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
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CCU_ADBASE_DI_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
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CCU_ADBASE_DI_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
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CCU_ADBASE_DI_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
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CCU_ADBASE_DI_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
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CCU_ADBASE_DI_MASK);
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/* this enables nonsecure access to DDR */
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/* mpuregion0addr_limit */
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FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
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FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
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/* nonmpuregion0addr_limit */
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FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
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FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
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FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
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/* Enable mpuregion0enable and nonmpuregion0enable */
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FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
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FW_MPU_DDR_SCR_EN_SET);
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/* Ensure HMC clock is running */
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if (poll_hmc_clock_status()) {
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puts("DDR: Error as HMC clock not running\n");
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return -1;
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}
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/* release DDR scheduler from reset */
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socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
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/* Try 3 times to do a calibration */
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for (i = 0; i < 3; i++) {
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ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
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DDRCALSTAT),
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DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
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false);
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if (!ret)
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break;
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emif_reset();
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}
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if (ret) {
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puts("DDR: Error as SDRAM calibration failed\n");
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return -1;
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}
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debug("DDR: Calibration success\n");
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u32 ctrlcfg0 = hmc_readl(CTRLCFG0);
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u32 ctrlcfg1 = hmc_readl(CTRLCFG1);
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u32 dramaddrw = hmc_readl(DRAMADDRW);
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u32 dramtim0 = hmc_readl(DRAMTIMING0);
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u32 caltim0 = hmc_readl(CALTIMING0);
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u32 caltim1 = hmc_readl(CALTIMING1);
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u32 caltim2 = hmc_readl(CALTIMING2);
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u32 caltim3 = hmc_readl(CALTIMING3);
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u32 caltim4 = hmc_readl(CALTIMING4);
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u32 caltim9 = hmc_readl(CALTIMING9);
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/*
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* Configure the DDR IO size [0xFFCFB008]
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* niosreserve0: Used to indicate DDR width &
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* bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
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* bit[8] = 1 if user-mode OCT is present
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* bit[9] = 1 if warm reset compiled into EMIF Cal Code
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* bit[10] = 1 if warm reset is on during generation in EMIF Cal
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* niosreserve1: IP ADCDS version encoded as 16 bit value
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* bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
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* 3=EAP, 4-6 are reserved)
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* bit[5:3] = Service Pack # (e.g. 1)
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* bit[9:6] = Minor Release #
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* bit[14:10] = Major Release #
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*/
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update_value = hmc_readl(NIOSRESERVED0);
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hmc_ecc_writel(((update_value & 0xFF) >> 5), DDRIOCTRL);
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ddrioctl = hmc_ecc_readl(DDRIOCTRL);
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/* enable HPS interface to HMC */
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hmc_ecc_writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
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/* Set the DDR Configuration */
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io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
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(DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
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DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
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DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
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update_value = match_ddr_conf(io48_value);
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if (update_value)
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ddr_sch_writel(update_value, DDR_SCH_DDRCONF);
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/* Configure HMC dramaddrw */
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hmc_ecc_writel(hmc_readl(DRAMADDRW), DRAMADDRWIDTH);
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/*
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* Configure DDR timing
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* RDTOMISS = tRTP + tRP + tRCD - BL/2
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* WRTOMISS = WL + tWR + tRP + tRCD and
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* WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
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* First part of equation is in memory clock units so divide by 2
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* for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
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* WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
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*/
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u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
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update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
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CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
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CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
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(burst_len >> 2);
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io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
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(burst_len >> 1)) >> 1) -
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/* Up to here was in memory cycles so divide by 2 */
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CALTIMING1_CFG_RD_TO_WR(caltim1) +
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CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
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CALTIMING4_CFG_PCH_TO_VALID(caltim4));
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ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
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DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
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(update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
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(io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
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((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
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(CALTIMING1_CFG_RD_TO_WR(caltim1) <<
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DDR_SCH_DDRTIMING_RDTOWR_OFF) |
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(CALTIMING3_CFG_WR_TO_RD(caltim3) <<
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DDR_SCH_DDRTIMING_WRTORD_OFF) |
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(((ddrioctl == 1) ? 1 : 0) <<
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DDR_SCH_DDRTIMING_BWRATIO_OFF)),
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DDR_SCH_DDRTIMING);
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/* Configure DDR mode [precharge = 0] */
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ddr_sch_writel(((ddrioctl ? 0 : 1) <<
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DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
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DDR_SCH_DDRMODE);
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/* Configure the read latency */
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ddr_sch_writel((DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
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DDR_READ_LATENCY_DELAY,
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DDR_SCH_READ_LATENCY);
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/*
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* Configuring timing values concerning activate commands
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* [FAWBANK alway 1 because always 4 bank DDR]
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*/
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ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
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DDR_SCH_ACTIVATE_RRD_OFF) |
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(CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
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DDR_SCH_ACTIVATE_FAW_OFF) |
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(DDR_ACTIVATE_FAWBANK <<
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DDR_SCH_ACTIVATE_FAWBANK_OFF)),
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DDR_SCH_ACTIVATE);
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/*
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* Configuring timing values concerning device to device data bus
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* ownership change
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*/
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ddr_sch_writel(((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
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DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
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(CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
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DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
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(CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
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DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
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DDR_SCH_DEVTODEV);
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/* assigning the SDRAM size */
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unsigned long long size = sdram_calculate_size();
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/* If the size is invalid, use default Config size */
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if (size <= 0)
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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else
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gd->ram_size = size;
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/* Enable or disable the SDRAM ECC */
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if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
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setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
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(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
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clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
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(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
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setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
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(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
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DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
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} else {
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clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
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(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
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clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
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(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
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DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
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}
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debug("DDR: HMC init success\n");
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return 0;
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}
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/**
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* sdram_calculate_size() - Calculate SDRAM size
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*
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* Calculate SDRAM device size based on SDRAM controller parameters.
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* Size is specified in bytes.
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*/
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phys_size_t sdram_calculate_size(void)
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{
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u32 dramaddrw = hmc_readl(DRAMADDRW);
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phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
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size *= (2 << (hmc_ecc_readl(DDRIOCTRL) &
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DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
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return size;
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}
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