upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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881 lines
23 KiB
881 lines
23 KiB
/*
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natsemi.c: A U-Boot driver for the NatSemi DP8381x series.
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Author: Mark A. Rakes (mark_rakes@vivato.net)
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Adapted from an Etherboot driver written by:
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Copyright (C) 2001 Entity Cyber, Inc.
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This development of this Etherboot driver was funded by
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Sicom Systems: http://www.sicompos.com/
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Author: Marty Connor (mdc@thinguin.org)
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Adapted from a Linux driver which was written by Donald Becker
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This software may be used and distributed according to the terms
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of the GNU Public License (GPL), incorporated herein by reference.
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Original Copyright Notice:
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Written/copyright 1999-2001 by Donald Becker.
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This software may be used and distributed according to the terms of
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the GNU General Public License (GPL), incorporated herein by reference.
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Drivers based on or derived from this code fall under the GPL and must
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retain the authorship, copyright and license notice. This file is not
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a complete program and may only be used when the entire operating
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system is licensed under the GPL. License for under other terms may be
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available. Contact the original author for details.
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The original author may be reached as becker@scyld.com, or at
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Scyld Computing Corporation
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410 Severn Ave., Suite 210
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Annapolis MD 21403
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Support information and updates available at
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http://www.scyld.com/network/netsemi.html
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References:
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http://www.scyld.com/expert/100mbps.html
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http://www.scyld.com/expert/NWay.html
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Datasheet is available from:
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http://www.national.com/pf/DP/DP83815.html
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*/
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/* Revision History
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* October 2002 mar 1.0
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* Initial U-Boot Release. Tested with Netgear FA311 board
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* and dp83815 chipset on custom board
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*/
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/* Includes */
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <asm/io.h>
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#include <pci.h>
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#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
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defined(CONFIG_NATSEMI)
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/* defines */
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#define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
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#define DSIZE 0x00000FFF
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#define ETH_ALEN 6
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#define CRC_SIZE 4
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#define TOUT_LOOP 500000
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#define TX_BUF_SIZE 1536
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#define RX_BUF_SIZE 1536
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#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
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/* Offsets to the device registers.
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Unlike software-only systems, device drivers interact with complex hardware.
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It's not useful to define symbolic names for every register bit in the
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device. */
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enum register_offsets {
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ChipCmd = 0x00,
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ChipConfig = 0x04,
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EECtrl = 0x08,
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IntrMask = 0x14,
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IntrEnable = 0x18,
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TxRingPtr = 0x20,
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TxConfig = 0x24,
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RxRingPtr = 0x30,
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RxConfig = 0x34,
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ClkRun = 0x3C,
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RxFilterAddr = 0x48,
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RxFilterData = 0x4C,
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SiliconRev = 0x58,
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PCIPM = 0x44,
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BasicControl = 0x80,
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BasicStatus = 0x84,
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/* These are from the spec, around page 78... on a separate table. */
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PGSEL = 0xCC,
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PMDCSR = 0xE4,
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TSTDAT = 0xFC,
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DSPCFG = 0xF4,
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SDCFG = 0x8C
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};
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/* Bit in ChipCmd. */
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enum ChipCmdBits {
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ChipReset = 0x100,
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RxReset = 0x20,
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TxReset = 0x10,
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RxOff = 0x08,
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RxOn = 0x04,
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TxOff = 0x02,
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TxOn = 0x01
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};
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enum ChipConfigBits {
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LinkSts = 0x80000000,
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HundSpeed = 0x40000000,
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FullDuplex = 0x20000000,
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TenPolarity = 0x10000000,
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AnegDone = 0x08000000,
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AnegEnBothBoth = 0x0000E000,
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AnegDis100Full = 0x0000C000,
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AnegEn100Both = 0x0000A000,
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AnegDis100Half = 0x00008000,
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AnegEnBothHalf = 0x00006000,
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AnegDis10Full = 0x00004000,
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AnegEn10Both = 0x00002000,
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DuplexMask = 0x00008000,
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SpeedMask = 0x00004000,
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AnegMask = 0x00002000,
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AnegDis10Half = 0x00000000,
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ExtPhy = 0x00001000,
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PhyRst = 0x00000400,
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PhyDis = 0x00000200,
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BootRomDisable = 0x00000004,
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BEMode = 0x00000001,
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};
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enum TxConfig_bits {
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TxDrthMask = 0x3f,
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TxFlthMask = 0x3f00,
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TxMxdmaMask = 0x700000,
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TxMxdma_512 = 0x0,
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TxMxdma_4 = 0x100000,
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TxMxdma_8 = 0x200000,
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TxMxdma_16 = 0x300000,
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TxMxdma_32 = 0x400000,
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TxMxdma_64 = 0x500000,
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TxMxdma_128 = 0x600000,
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TxMxdma_256 = 0x700000,
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TxCollRetry = 0x800000,
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TxAutoPad = 0x10000000,
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TxMacLoop = 0x20000000,
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TxHeartIgn = 0x40000000,
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TxCarrierIgn = 0x80000000
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};
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enum RxConfig_bits {
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RxDrthMask = 0x3e,
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RxMxdmaMask = 0x700000,
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RxMxdma_512 = 0x0,
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RxMxdma_4 = 0x100000,
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RxMxdma_8 = 0x200000,
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RxMxdma_16 = 0x300000,
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RxMxdma_32 = 0x400000,
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RxMxdma_64 = 0x500000,
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RxMxdma_128 = 0x600000,
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RxMxdma_256 = 0x700000,
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RxAcceptLong = 0x8000000,
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RxAcceptTx = 0x10000000,
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RxAcceptRunt = 0x40000000,
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RxAcceptErr = 0x80000000
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};
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/* Bits in the RxMode register. */
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enum rx_mode_bits {
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AcceptErr = 0x20,
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AcceptRunt = 0x10,
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AcceptBroadcast = 0xC0000000,
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AcceptMulticast = 0x00200000,
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AcceptAllMulticast = 0x20000000,
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AcceptAllPhys = 0x10000000,
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AcceptMyPhys = 0x08000000
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};
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typedef struct _BufferDesc {
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u32 link;
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vu_long cmdsts;
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u32 bufptr;
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u32 software_use;
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} BufferDesc;
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/* Bits in network_desc.status */
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enum desc_status_bits {
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DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
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DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
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DescSizeMask = 0xfff,
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DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
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DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
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DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
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DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
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DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
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DescRxDest = 0x01800000, DescRxLong = 0x00400000,
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DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
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DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
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DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
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};
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/* Globals */
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#ifdef NATSEMI_DEBUG
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static int natsemi_debug = 0; /* 1 verbose debugging, 0 normal */
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#endif
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static u32 SavedClkRun;
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static unsigned int cur_rx;
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static unsigned int advertising;
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static unsigned int rx_config;
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static unsigned int tx_config;
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/* Note: transmit and receive buffers and descriptors must be
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longword aligned */
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static BufferDesc txd __attribute__ ((aligned(4)));
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static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4)));
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static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4)));
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static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
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__attribute__ ((aligned(4)));
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/* Function Prototypes */
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#if 0
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static void write_eeprom(struct eth_device *dev, long addr, int location,
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short value);
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#endif
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static int read_eeprom(struct eth_device *dev, long addr, int location);
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static int mdio_read(struct eth_device *dev, int phy_id, int location);
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static int natsemi_init(struct eth_device *dev, bd_t * bis);
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static void natsemi_reset(struct eth_device *dev);
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static void natsemi_init_rxfilter(struct eth_device *dev);
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static void natsemi_init_txd(struct eth_device *dev);
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static void natsemi_init_rxd(struct eth_device *dev);
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static void natsemi_set_rx_mode(struct eth_device *dev);
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static void natsemi_check_duplex(struct eth_device *dev);
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static int natsemi_send(struct eth_device *dev, volatile void *packet,
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int length);
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static int natsemi_poll(struct eth_device *dev);
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static void natsemi_disable(struct eth_device *dev);
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static struct pci_device_id supported[] = {
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{PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815},
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{}
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};
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#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
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#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
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static inline int
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INW(struct eth_device *dev, u_long addr)
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{
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return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
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}
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static int
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INL(struct eth_device *dev, u_long addr)
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{
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return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
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}
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static inline void
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OUTW(struct eth_device *dev, int command, u_long addr)
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{
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*(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
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}
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static inline void
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OUTL(struct eth_device *dev, int command, u_long addr)
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{
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*(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
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}
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/*
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* Function: natsemi_initialize
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*
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* Description: Retrieves the MAC address of the card, and sets up some
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* globals required by other routines, and initializes the NIC, making it
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* ready to send and receive packets.
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*
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* Side effects:
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* leaves the natsemi initialized, and ready to recieve packets.
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*
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* Returns: struct eth_device *: pointer to NIC data structure
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*/
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int
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natsemi_initialize(bd_t * bis)
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{
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pci_dev_t devno;
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int card_number = 0;
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struct eth_device *dev;
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u32 iobase, status, chip_config;
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int i, idx = 0;
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int prev_eedata;
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u32 tmp;
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while (1) {
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/* Find PCI device(s) */
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if ((devno = pci_find_devices(supported, idx++)) < 0) {
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break;
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}
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pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
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iobase &= ~0xF; /* Masked out the low bits that are addresses. */
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pci_write_config_dword(devno, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* Check if I/O accesses and Bus Mastering are enabled. */
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pci_read_config_dword(devno, PCI_COMMAND, &status);
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if (!(status & PCI_COMMAND_MEMORY)) {
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printf("Error: Can not enable MEM access.\n");
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continue;
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} else if (!(status & PCI_COMMAND_MASTER)) {
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printf("Error: Can not enable Bus Mastering.\n");
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continue;
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}
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dev = (struct eth_device *) malloc(sizeof *dev);
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sprintf(dev->name, "dp83815#%d", card_number);
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dev->iobase = bus_to_phys(iobase);
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#ifdef NATSEMI_DEBUG
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printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase);
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#endif
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dev->priv = (void *) devno;
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dev->init = natsemi_init;
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dev->halt = natsemi_disable;
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dev->send = natsemi_send;
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dev->recv = natsemi_poll;
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eth_register(dev);
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card_number++;
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/* Set the latency timer for value. */
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pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
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udelay(10 * 1000);
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/* natsemi has a non-standard PM control register
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* in PCI config space. Some boards apparently need
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* to be brought to D0 in this manner. */
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pci_read_config_dword(devno, PCIPM, &tmp);
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if (tmp & (0x03 | 0x100)) {
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/* D0 state, disable PME assertion */
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u32 newtmp = tmp & ~(0x03 | 0x100);
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pci_write_config_dword(devno, PCIPM, newtmp);
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}
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printf("natsemi: EEPROM contents:\n");
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for (i = 0; i <= EEPROM_SIZE; i++) {
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short eedata = read_eeprom(dev, EECtrl, i);
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printf(" %04hx", eedata);
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}
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printf("\n");
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/* get MAC address */
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prev_eedata = read_eeprom(dev, EECtrl, 6);
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for (i = 0; i < 3; i++) {
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int eedata = read_eeprom(dev, EECtrl, i + 7);
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dev->enetaddr[i*2] = (eedata << 1) + (prev_eedata >> 15);
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dev->enetaddr[i*2+1] = eedata >> 7;
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prev_eedata = eedata;
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}
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/* Reset the chip to erase any previous misconfiguration. */
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OUTL(dev, ChipReset, ChipCmd);
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advertising = mdio_read(dev, 1, 4);
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chip_config = INL(dev, ChipConfig);
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#ifdef NATSEMI_DEBUG
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printf("%s: Transceiver status %#08X advertising %#08X\n",
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dev->name, (int) INL(dev, BasicStatus), advertising);
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printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n",
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dev->name, chip_config & AnegMask ? "enabled, advertise" :
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"disabled, force", chip_config & SpeedMask ? "0" : "",
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chip_config & DuplexMask ? "full" : "half");
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#endif
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chip_config |= AnegEnBothBoth;
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#ifdef NATSEMI_DEBUG
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printf("%s: changed to autoneg. %s 10%s %s duplex.\n",
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dev->name, chip_config & AnegMask ? "enabled, advertise" :
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"disabled, force", chip_config & SpeedMask ? "0" : "",
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chip_config & DuplexMask ? "full" : "half");
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#endif
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/*write new autoneg bits, reset phy*/
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OUTL(dev, (chip_config | PhyRst), ChipConfig);
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/*un-reset phy*/
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OUTL(dev, chip_config, ChipConfig);
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/* Disable PME:
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* The PME bit is initialized from the EEPROM contents.
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* PCI cards probably have PME disabled, but motherboard
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* implementations may have PME set to enable WakeOnLan.
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* With PME set the chip will scan incoming packets but
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* nothing will be written to memory. */
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SavedClkRun = INL(dev, ClkRun);
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OUTL(dev, SavedClkRun & ~0x100, ClkRun);
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}
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return card_number;
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}
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/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
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The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */
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/* Delay between EEPROM clock transitions.
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No extra delay is needed with 33Mhz PCI, but future 66Mhz
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access may need a delay. */
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#define eeprom_delay(ee_addr) INL(dev, ee_addr)
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enum EEPROM_Ctrl_Bits {
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EE_ShiftClk = 0x04,
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EE_DataIn = 0x01,
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EE_ChipSelect = 0x08,
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EE_DataOut = 0x02
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};
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#define EE_Write0 (EE_ChipSelect)
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#define EE_Write1 (EE_ChipSelect | EE_DataIn)
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/* The EEPROM commands include the alway-set leading bit. */
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enum EEPROM_Cmds {
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EE_WrEnCmd = (4 << 6), EE_WriteCmd = (5 << 6),
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EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6),
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};
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#if 0
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static void
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write_eeprom(struct eth_device *dev, long addr, int location, short value)
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{
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int i;
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int ee_addr = (typeof(ee_addr))addr;
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short wren_cmd = EE_WrEnCmd | 0x30; /*wren is 100 + 11XXXX*/
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short write_cmd = location | EE_WriteCmd;
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#ifdef NATSEMI_DEBUG
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printf("write_eeprom: %08x, %04hx, %04hx\n",
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dev->iobase + ee_addr, write_cmd, value);
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#endif
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/* Shift the write enable command bits out. */
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for (i = 9; i >= 0; i--) {
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short cmdval = (wren_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
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OUTL(dev, cmdval, ee_addr);
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eeprom_delay(ee_addr);
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OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
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eeprom_delay(ee_addr);
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}
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OUTL(dev, 0, ee_addr); /*bring chip select low*/
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OUTL(dev, EE_ShiftClk, ee_addr);
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eeprom_delay(ee_addr);
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/* Shift the write command bits out. */
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for (i = 9; i >= 0; i--) {
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short cmdval = (write_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
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OUTL(dev, cmdval, ee_addr);
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eeprom_delay(ee_addr);
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OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
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eeprom_delay(ee_addr);
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}
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for (i = 0; i < 16; i++) {
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short cmdval = (value & (1 << i)) ? EE_Write1 : EE_Write0;
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OUTL(dev, cmdval, ee_addr);
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eeprom_delay(ee_addr);
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OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
|
|
eeprom_delay(ee_addr);
|
|
}
|
|
|
|
OUTL(dev, 0, ee_addr); /*bring chip select low*/
|
|
OUTL(dev, EE_ShiftClk, ee_addr);
|
|
for (i = 0; i < 200000; i++) {
|
|
OUTL(dev, EE_Write0, ee_addr); /*poll for done*/
|
|
if (INL(dev, ee_addr) & EE_DataOut) {
|
|
break; /*finished*/
|
|
}
|
|
}
|
|
eeprom_delay(ee_addr);
|
|
|
|
/* Terminate the EEPROM access. */
|
|
OUTL(dev, EE_Write0, ee_addr);
|
|
OUTL(dev, 0, ee_addr);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
static int
|
|
read_eeprom(struct eth_device *dev, long addr, int location)
|
|
{
|
|
int i;
|
|
int retval = 0;
|
|
int ee_addr = (typeof(ee_addr))addr;
|
|
int read_cmd = location | EE_ReadCmd;
|
|
|
|
OUTL(dev, EE_Write0, ee_addr);
|
|
|
|
/* Shift the read command bits out. */
|
|
for (i = 10; i >= 0; i--) {
|
|
short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
|
|
OUTL(dev, dataval, ee_addr);
|
|
eeprom_delay(ee_addr);
|
|
OUTL(dev, dataval | EE_ShiftClk, ee_addr);
|
|
eeprom_delay(ee_addr);
|
|
}
|
|
OUTL(dev, EE_ChipSelect, ee_addr);
|
|
eeprom_delay(ee_addr);
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
OUTL(dev, EE_ChipSelect | EE_ShiftClk, ee_addr);
|
|
eeprom_delay(ee_addr);
|
|
retval |= (INL(dev, ee_addr) & EE_DataOut) ? 1 << i : 0;
|
|
OUTL(dev, EE_ChipSelect, ee_addr);
|
|
eeprom_delay(ee_addr);
|
|
}
|
|
|
|
/* Terminate the EEPROM access. */
|
|
OUTL(dev, EE_Write0, ee_addr);
|
|
OUTL(dev, 0, ee_addr);
|
|
#ifdef NATSEMI_DEBUG
|
|
if (natsemi_debug)
|
|
printf("read_eeprom: %08x, %08x, retval %08x\n",
|
|
dev->iobase + ee_addr, read_cmd, retval);
|
|
#endif
|
|
return retval;
|
|
}
|
|
|
|
/* MII transceiver control section.
|
|
The 83815 series has an internal transceiver, and we present the
|
|
management registers as if they were MII connected. */
|
|
|
|
static int
|
|
mdio_read(struct eth_device *dev, int phy_id, int location)
|
|
{
|
|
if (phy_id == 1 && location < 32)
|
|
return INL(dev, BasicControl+(location<<2))&0xffff;
|
|
else
|
|
return 0xffff;
|
|
}
|
|
|
|
/* Function: natsemi_init
|
|
*
|
|
* Description: resets the ethernet controller chip and configures
|
|
* registers and data structures required for sending and receiving packets.
|
|
*
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
*
|
|
* returns: int.
|
|
*/
|
|
|
|
static int
|
|
natsemi_init(struct eth_device *dev, bd_t * bis)
|
|
{
|
|
|
|
natsemi_reset(dev);
|
|
|
|
/* Disable PME:
|
|
* The PME bit is initialized from the EEPROM contents.
|
|
* PCI cards probably have PME disabled, but motherboard
|
|
* implementations may have PME set to enable WakeOnLan.
|
|
* With PME set the chip will scan incoming packets but
|
|
* nothing will be written to memory. */
|
|
OUTL(dev, SavedClkRun & ~0x100, ClkRun);
|
|
|
|
natsemi_init_rxfilter(dev);
|
|
natsemi_init_txd(dev);
|
|
natsemi_init_rxd(dev);
|
|
|
|
/* Configure the PCI bus bursts and FIFO thresholds. */
|
|
tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002);
|
|
rx_config = RxMxdma_256 | 0x20;
|
|
|
|
#ifdef NATSEMI_DEBUG
|
|
printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
|
|
printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
|
|
#endif
|
|
OUTL(dev, tx_config, TxConfig);
|
|
OUTL(dev, rx_config, RxConfig);
|
|
|
|
natsemi_check_duplex(dev);
|
|
natsemi_set_rx_mode(dev);
|
|
|
|
OUTL(dev, (RxOn | TxOn), ChipCmd);
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* Function: natsemi_reset
|
|
*
|
|
* Description: soft resets the controller chip
|
|
*
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
*
|
|
* Returns: void.
|
|
*/
|
|
static void
|
|
natsemi_reset(struct eth_device *dev)
|
|
{
|
|
OUTL(dev, ChipReset, ChipCmd);
|
|
|
|
/* On page 78 of the spec, they recommend some settings for "optimum
|
|
performance" to be done in sequence. These settings optimize some
|
|
of the 100Mbit autodetection circuitry. Also, we only want to do
|
|
this for rev C of the chip. */
|
|
if (INL(dev, SiliconRev) == 0x302) {
|
|
OUTW(dev, 0x0001, PGSEL);
|
|
OUTW(dev, 0x189C, PMDCSR);
|
|
OUTW(dev, 0x0000, TSTDAT);
|
|
OUTW(dev, 0x5040, DSPCFG);
|
|
OUTW(dev, 0x008C, SDCFG);
|
|
}
|
|
/* Disable interrupts using the mask. */
|
|
OUTL(dev, 0, IntrMask);
|
|
OUTL(dev, 0, IntrEnable);
|
|
}
|
|
|
|
/* Function: natsemi_init_rxfilter
|
|
*
|
|
* Description: sets receive filter address to our MAC address
|
|
*
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
*
|
|
* returns: void.
|
|
*/
|
|
|
|
static void
|
|
natsemi_init_rxfilter(struct eth_device *dev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ETH_ALEN; i += 2) {
|
|
OUTL(dev, i, RxFilterAddr);
|
|
OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
|
|
RxFilterData);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Function: natsemi_init_txd
|
|
*
|
|
* Description: initializes the Tx descriptor
|
|
*
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
*
|
|
* returns: void.
|
|
*/
|
|
|
|
static void
|
|
natsemi_init_txd(struct eth_device *dev)
|
|
{
|
|
txd.link = (u32) 0;
|
|
txd.cmdsts = (u32) 0;
|
|
txd.bufptr = (u32) & txb[0];
|
|
|
|
/* load Transmit Descriptor Register */
|
|
OUTL(dev, (u32) & txd, TxRingPtr);
|
|
#ifdef NATSEMI_DEBUG
|
|
printf("natsemi_init_txd: TX descriptor reg loaded with: %#08X\n",
|
|
INL(dev, TxRingPtr));
|
|
#endif
|
|
}
|
|
|
|
/* Function: natsemi_init_rxd
|
|
*
|
|
* Description: initializes the Rx descriptor ring
|
|
*
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
*
|
|
* Returns: void.
|
|
*/
|
|
|
|
static void
|
|
natsemi_init_rxd(struct eth_device *dev)
|
|
{
|
|
int i;
|
|
|
|
cur_rx = 0;
|
|
|
|
/* init RX descriptor */
|
|
for (i = 0; i < NUM_RX_DESC; i++) {
|
|
rxd[i].link =
|
|
cpu_to_le32((i + 1 <
|
|
NUM_RX_DESC) ? (u32) & rxd[i +
|
|
1] : (u32) &
|
|
rxd[0]);
|
|
rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
|
|
rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
|
|
#ifdef NATSEMI_DEBUG
|
|
printf
|
|
("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n",
|
|
i, &rxd[i], le32_to_cpu(rxd[i].link),
|
|
rxd[i].cmdsts, rxd[i].bufptr);
|
|
#endif
|
|
}
|
|
|
|
/* load Receive Descriptor Register */
|
|
OUTL(dev, (u32) & rxd[0], RxRingPtr);
|
|
|
|
#ifdef NATSEMI_DEBUG
|
|
printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n",
|
|
INL(dev, RxRingPtr));
|
|
#endif
|
|
}
|
|
|
|
/* Function: natsemi_set_rx_mode
|
|
*
|
|
* Description:
|
|
* sets the receive mode to accept all broadcast packets and packets
|
|
* with our MAC address, and reject all multicast packets.
|
|
*
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
*
|
|
* Returns: void.
|
|
*/
|
|
|
|
static void
|
|
natsemi_set_rx_mode(struct eth_device *dev)
|
|
{
|
|
u32 rx_mode = AcceptBroadcast | AcceptMyPhys;
|
|
|
|
OUTL(dev, rx_mode, RxFilterAddr);
|
|
}
|
|
|
|
static void
|
|
natsemi_check_duplex(struct eth_device *dev)
|
|
{
|
|
int duplex = INL(dev, ChipConfig) & FullDuplex ? 1 : 0;
|
|
|
|
#ifdef NATSEMI_DEBUG
|
|
printf("%s: Setting %s-duplex based on negotiated link"
|
|
" capability.\n", dev->name, duplex ? "full" : "half");
|
|
#endif
|
|
if (duplex) {
|
|
rx_config |= RxAcceptTx;
|
|
tx_config |= (TxCarrierIgn | TxHeartIgn);
|
|
} else {
|
|
rx_config &= ~RxAcceptTx;
|
|
tx_config &= ~(TxCarrierIgn | TxHeartIgn);
|
|
}
|
|
OUTL(dev, tx_config, TxConfig);
|
|
OUTL(dev, rx_config, RxConfig);
|
|
}
|
|
|
|
/* Function: natsemi_send
|
|
*
|
|
* Description: transmits a packet and waits for completion or timeout.
|
|
*
|
|
* Returns: void. */
|
|
static int
|
|
natsemi_send(struct eth_device *dev, volatile void *packet, int length)
|
|
{
|
|
u32 i, status = 0;
|
|
u32 tx_status = 0;
|
|
|
|
/* Stop the transmitter */
|
|
OUTL(dev, TxOff, ChipCmd);
|
|
|
|
#ifdef NATSEMI_DEBUG
|
|
if (natsemi_debug)
|
|
printf("natsemi_send: sending %d bytes\n", (int) length);
|
|
#endif
|
|
|
|
/* set the transmit buffer descriptor and enable Transmit State Machine */
|
|
txd.link = cpu_to_le32(0);
|
|
txd.bufptr = cpu_to_le32(phys_to_bus((u32) packet));
|
|
txd.cmdsts = cpu_to_le32(DescOwn | length);
|
|
|
|
/* load Transmit Descriptor Register */
|
|
OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
|
|
#ifdef NATSEMI_DEBUG
|
|
if (natsemi_debug)
|
|
printf("natsemi_send: TX descriptor register loaded with: %#08X\n",
|
|
INL(dev, TxRingPtr));
|
|
#endif
|
|
/* restart the transmitter */
|
|
OUTL(dev, TxOn, ChipCmd);
|
|
|
|
for (i = 0;
|
|
((vu_long)tx_status = le32_to_cpu(txd.cmdsts)) & DescOwn;
|
|
i++) {
|
|
if (i >= TOUT_LOOP) {
|
|
printf
|
|
("%s: tx error buffer not ready: txd.cmdsts == %#X\n",
|
|
dev->name, tx_status);
|
|
goto Done;
|
|
}
|
|
}
|
|
|
|
if (!(tx_status & DescPktOK)) {
|
|
printf("natsemi_send: Transmit error, Tx status %X.\n",
|
|
tx_status);
|
|
goto Done;
|
|
}
|
|
|
|
status = 1;
|
|
Done:
|
|
return status;
|
|
}
|
|
|
|
/* Function: natsemi_poll
|
|
*
|
|
* Description: checks for a received packet and returns it if found.
|
|
*
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
*
|
|
* Returns: 1 if packet was received.
|
|
* 0 if no packet was received.
|
|
*
|
|
* Side effects:
|
|
* Returns (copies) the packet to the array dev->packet.
|
|
* Returns the length of the packet.
|
|
*/
|
|
|
|
static int
|
|
natsemi_poll(struct eth_device *dev)
|
|
{
|
|
int retstat = 0;
|
|
int length = 0;
|
|
u32 rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
|
|
|
|
if (!(rx_status & (u32) DescOwn))
|
|
return retstat;
|
|
#ifdef NATSEMI_DEBUG
|
|
if (natsemi_debug)
|
|
printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n",
|
|
cur_rx, rx_status);
|
|
#endif
|
|
length = (rx_status & DSIZE) - CRC_SIZE;
|
|
|
|
if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
|
|
printf
|
|
("natsemi_poll: Corrupted packet received, buffer status = %X\n",
|
|
rx_status);
|
|
retstat = 0;
|
|
} else { /* give packet to higher level routine */
|
|
NetReceive((rxb + cur_rx * RX_BUF_SIZE), length);
|
|
retstat = 1;
|
|
}
|
|
|
|
/* return the descriptor and buffer to receive ring */
|
|
rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
|
|
rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
|
|
|
|
if (++cur_rx == NUM_RX_DESC)
|
|
cur_rx = 0;
|
|
|
|
/* re-enable the potentially idle receive state machine */
|
|
OUTL(dev, RxOn, ChipCmd);
|
|
|
|
return retstat;
|
|
}
|
|
|
|
/* Function: natsemi_disable
|
|
*
|
|
* Description: Turns off interrupts and stops Tx and Rx engines
|
|
*
|
|
* Arguments: struct eth_device *dev: NIC data structure
|
|
*
|
|
* Returns: void.
|
|
*/
|
|
|
|
static void
|
|
natsemi_disable(struct eth_device *dev)
|
|
{
|
|
/* Disable interrupts using the mask. */
|
|
OUTL(dev, 0, IntrMask);
|
|
OUTL(dev, 0, IntrEnable);
|
|
|
|
/* Stop the chip's Tx and Rx processes. */
|
|
OUTL(dev, RxOff | TxOff, ChipCmd);
|
|
|
|
/* Restore PME enable bit */
|
|
OUTL(dev, SavedClkRun, ClkRun);
|
|
}
|
|
|
|
#endif
|
|
|