upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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53 lines
1.2 KiB
53 lines
1.2 KiB
/*
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* Keystone2: DDR3 initialization
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include "ddr3_cfg.h"
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#include <asm/arch/ddr3.h>
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static struct pll_init_data ddr3_400 = DDR3_PLL_400;
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u32 ddr3_init(void)
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{
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u32 ddr3_size;
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char dimm_name[32];
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if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
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init_pll(&ddr3_400);
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ddr3_get_dimm_params(dimm_name);
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printf("Detected SO-DIMM [%s]\n", dimm_name);
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/* Reset DDR3 PHY after PLL enabled */
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ddr3_reset_ddrphy();
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if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
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/* 8G SO-DIMM */
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ddr3_size = 8;
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printf("DRAM: 8 GiB\n");
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ddr3phy_1600_8g.zq0cr1 |= 0x10000;
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ddr3phy_1600_8g.zq1cr1 |= 0x10000;
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ddr3phy_1600_8g.zq2cr1 |= 0x10000;
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
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ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
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} else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
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/* 4G SO-DIMM */
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ddr3_size = 4;
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printf("DRAM: 4 GiB\n");
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
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ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
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} else {
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printf("Unknown SO-DIMM. Cannot configure DDR3\n");
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while (1)
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;
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}
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return ddr3_size;
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}
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