upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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70 lines
4.1 KiB
70 lines
4.1 KiB
/*
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* Enhanced PPI (EPPI)
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*/
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#ifndef __BFIN_PERIPHERAL_EPPI__
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#define __BFIN_PERIPHERAL_EPPI__
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/* Bit masks for EPPIx_STATUS */
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#define CFIFO_ERR 0x0001 /* Chroma FIFO Error */
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#define YFIFO_ERR 0x0002 /* Luma FIFO Error */
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#define LTERR_OVR 0x0004 /* Line Track Overflow */
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#define LTERR_UNDR 0x0008 /* Line Track Underflow */
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#define FTERR_OVR 0x0010 /* Frame Track Overflow */
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#define FTERR_UNDR 0x0020 /* Frame Track Underflow */
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#define ERR_NCOR 0x0040 /* Preamble Error Not Corrected */
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#define DMA1URQ 0x0080 /* DMA1 Urgent Request */
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#define DMA0URQ 0x0100 /* DMA0 Urgent Request */
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#define ERR_DET 0x4000 /* Preamble Error Detected */
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#define FLD 0x8000 /* Field */
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/* Bit masks for EPPIx_CONTROL */
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#define EPPI_EN 0x00000001 /* Enable */
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#define EPPI_DIR 0x00000002 /* Direction */
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#define XFR_TYPE 0x0000000c /* Operating Mode */
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#define FS_CFG 0x00000030 /* Frame Sync Configuration */
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#define FLD_SEL 0x00000040 /* Field Select/Trigger */
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#define ITU_TYPE 0x00000080 /* ITU Interlaced or Progressive */
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#define BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
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#define ICLKGEN 0x00000200 /* Internal Clock Generation */
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#define IFSGEN 0x00000400 /* Internal Frame Sync Generation */
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#define POLC 0x00001800 /* Frame Sync and Data Driving/Sampling Edges */
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#define POLS 0x00006000 /* Frame Sync Polarity */
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#define DLENGTH 0x00038000 /* Data Length */
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#define SKIP_EN 0x00040000 /* Skip Enable */
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#define SKIP_EO 0x00080000 /* Skip Even or Odd */
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#define PACKEN 0x00100000 /* Packing/Unpacking Enable */
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#define SWAPEN 0x00200000 /* Swap Enable */
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#define SIGN_EXT 0x00400000 /* Sign Extension or Zero-filled / Data Split Format */
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#define SPLT_EVEN_ODD 0x00800000 /* Split Even and Odd Data Samples */
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#define SUBSPLT_ODD 0x01000000 /* Sub-split Odd Samples */
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#define DMACFG 0x02000000 /* One or Two DMA Channels Mode */
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#define RGB_FMT_EN 0x04000000 /* RGB Formatting Enable */
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#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
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#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
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#define DLEN_8 (0 << 15) /* 000 - 8 bits */
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#define DLEN_10 (1 << 15) /* 001 - 10 bits */
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#define DLEN_12 (2 << 15) /* 010 - 12 bits */
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#define DLEN_14 (3 << 15) /* 011 - 14 bits */
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#define DLEN_16 (4 << 15) /* 100 - 16 bits */
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#define DLEN_18 (5 << 15) /* 101 - 18 bits */
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#define DLEN_24 (6 << 15) /* 110 - 24 bits */
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/* Bit masks for EPPIx_FS2W_LVB */
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#define F1VB_BD 0x000000ff /* Vertical Blanking before Field 1 Active Data */
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#define F1VB_AD 0x0000ff00 /* Vertical Blanking after Field 1 Active Data */
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#define F2VB_BD 0x00ff0000 /* Vertical Blanking before Field 2 Active Data */
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#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */
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/* Bit masks for EPPIx_FS2W_LAVF */
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#define F1_ACT 0x0000ffff /* Number of Lines of Active Data in Field 1 */
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#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */
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/* Bit masks for EPPIx_CLIP */
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#define LOW_ODD 0x000000ff /* Lower Limit for Odd Bytes (Chroma) */
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#define HIGH_ODD 0x0000ff00 /* Upper Limit for Odd Bytes (Chroma) */
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#define LOW_EVEN 0x00ff0000 /* Lower Limit for Even Bytes (Luma) */
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#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
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#endif
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