upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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257 lines
6.4 KiB
257 lines
6.4 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
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*
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* based on the files by
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* Sascha Hauer, Pengutronix
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*/
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#include <common.h>
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#include <environment.h>
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#include <jffs2/jffs2.h>
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#include <nand.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include <linux/errno.h>
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#include "apf27.h"
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#include "crc.h"
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#include "fpga.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Fuse bank 1 row 8 is "reserved for future use" and therefore available for
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* customer use. The APF27 board uses this fuse to store the board revision:
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* 0: initial board revision
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* 1: first revision - Presence of the second RAM chip on the board is blown in
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* fuse bank 1 row 9 bit 0 - No hardware change
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* N: to be defined
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*/
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static u32 get_board_rev(void)
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{
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struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
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return readl(&iim->bank[1].fuse_regs[8]);
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}
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/*
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* Fuse bank 1 row 9 is "reserved for future use" and therefore available for
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* customer use. The APF27 board revision 1 uses the bit 0 to permanently store
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* the presence of the second RAM chip
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* 0: AFP27 with 1 RAM of 64 MiB
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* 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
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*/
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static int get_num_ram_bank(void)
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{
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struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
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int nr_dram_banks = 1;
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if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
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nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01;
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else
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nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
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return nr_dram_banks;
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}
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static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2,
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u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2,
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u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr,
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u32 puen, u32 gius)
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{
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struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
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writel(gpio_dr, ®s->port[port].gpio_dr);
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writel(ocr1, ®s->port[port].ocr1);
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writel(ocr2, ®s->port[port].ocr2);
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writel(iconfa1, ®s->port[port].iconfa1);
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writel(iconfa2, ®s->port[port].iconfa2);
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writel(iconfb1, ®s->port[port].iconfb1);
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writel(iconfb2, ®s->port[port].iconfb2);
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writel(icr1, ®s->port[port].icr1);
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writel(icr2, ®s->port[port].icr2);
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writel(imr, ®s->port[port].imr);
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writel(gpio_dir, ®s->port[port].gpio_dir);
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writel(gpr, ®s->port[port].gpr);
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writel(puen, ®s->port[port].puen);
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writel(gius, ®s->port[port].gius);
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}
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#define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL, \
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ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL, \
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ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \
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ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL, \
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ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL, \
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ACFG_GIUS_##n##_VAL)
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static void apf27_iomux_init(void)
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{
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APF27_PORT_INIT(A);
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APF27_PORT_INIT(B);
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APF27_PORT_INIT(C);
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APF27_PORT_INIT(D);
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APF27_PORT_INIT(E);
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APF27_PORT_INIT(F);
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}
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static int apf27_devices_init(void)
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{
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int i;
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unsigned int mode[] = {
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PC5_PF_I2C2_DATA,
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PC6_PF_I2C2_CLK,
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PD17_PF_I2C_DATA,
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PD18_PF_I2C_CLK,
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};
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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#ifdef CONFIG_MXC_UART
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mx27_uart1_init_pins();
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#endif
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#ifdef CONFIG_FEC_MXC
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mx27_fec_init_pins();
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#endif
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#ifdef CONFIG_MMC_MXC
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mx27_sd2_init_pins();
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imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16));
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gpio_request(PC_PWRON, "pc_pwron");
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gpio_set_value(PC_PWRON, 1);
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#endif
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return 0;
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}
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static void apf27_setup_csx(void)
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{
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struct weim_regs *weim = (struct weim_regs *)IMX_WEIM_BASE;
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writel(ACFG_CS0U_VAL, &weim->cs0u);
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writel(ACFG_CS0L_VAL, &weim->cs0l);
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writel(ACFG_CS0A_VAL, &weim->cs0a);
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writel(ACFG_CS1U_VAL, &weim->cs1u);
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writel(ACFG_CS1L_VAL, &weim->cs1l);
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writel(ACFG_CS1A_VAL, &weim->cs1a);
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writel(ACFG_CS2U_VAL, &weim->cs2u);
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writel(ACFG_CS2L_VAL, &weim->cs2l);
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writel(ACFG_CS2A_VAL, &weim->cs2a);
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writel(ACFG_CS3U_VAL, &weim->cs3u);
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writel(ACFG_CS3L_VAL, &weim->cs3l);
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writel(ACFG_CS3A_VAL, &weim->cs3a);
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writel(ACFG_CS4U_VAL, &weim->cs4u);
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writel(ACFG_CS4L_VAL, &weim->cs4l);
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writel(ACFG_CS4A_VAL, &weim->cs4a);
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writel(ACFG_CS5U_VAL, &weim->cs5u);
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writel(ACFG_CS5L_VAL, &weim->cs5l);
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writel(ACFG_CS5A_VAL, &weim->cs5a);
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writel(ACFG_EIM_VAL, &weim->eim);
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}
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static void apf27_setup_port(void)
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{
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struct system_control_regs *system =
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(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
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writel(ACFG_FMCR_VAL, &system->fmcr);
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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apf27_setup_csx();
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apf27_setup_port();
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apf27_iomux_init();
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apf27_devices_init();
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#if defined(CONFIG_FPGA)
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APF27_init_fpga();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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if (get_num_ram_bank() > 1)
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gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
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PHYS_SDRAM_2_SIZE);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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if (get_num_ram_bank() > 1)
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gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
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PHYS_SDRAM_2_SIZE);
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else
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gd->bd->bi_dram[1].size = 0;
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return 0;
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}
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ulong board_get_usable_ram_top(ulong total_size)
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{
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ulong ramtop;
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if (get_num_ram_bank() > 1)
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ramtop = PHYS_SDRAM_2 + get_ram_size((void *)PHYS_SDRAM_2,
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PHYS_SDRAM_2_SIZE);
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else
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ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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return ramtop;
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}
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int checkboard(void)
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{
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printf("Board: Armadeus APF27 revision %d\n", get_board_rev());
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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inline void hang(void)
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{
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for (;;)
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;
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}
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void board_init_f(ulong bootflag)
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{
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/*
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* copy ourselves from where we are running to where we were
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* linked at. Use ulong pointers as all addresses involved
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* are 4-byte-aligned.
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*/
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ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
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asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
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asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
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asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
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asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
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for (dst = start_ptr; dst < end_ptr; dst++)
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*dst = *(dst+(run_ptr-link_ptr));
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/*
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* branch to nand_boot's link-time address.
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*/
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asm volatile("ldr pc, =nand_boot");
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}
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#endif /* CONFIG_SPL_BUILD */
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