upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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520 lines
13 KiB
520 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/bcm63xx/cpu.c:
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#define REV_CHIPID_SHIFT 16
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#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
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#define REV_LONG_CHIPID_SHIFT 12
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#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT)
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#define REV_REVID_SHIFT 0
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#define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
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#define REG_BCM6328_OTP 0x62c
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#define BCM6328_TP1_DISABLED BIT(9)
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#define REG_BCM6318_STRAP_OVRDBUS 0x900
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#define OVRDBUS_6318_FREQ_SHIFT 23
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#define OVRDBUS_6318_FREQ_MASK (0x3 << OVRDBUS_6318_FREQ_SHIFT)
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#define REG_BCM6328_MISC_STRAPBUS 0x1a40
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#define STRAPBUS_6328_FCVO_SHIFT 7
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#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
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#define REG_BCM6348_PERF_MIPSPLLCFG 0x34
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#define MIPSPLLCFG_6348_M1CPU_SHIFT 6
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#define MIPSPLLCFG_6348_M1CPU_MASK (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
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#define MIPSPLLCFG_6348_N2_SHIFT 15
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#define MIPSPLLCFG_6348_N2_MASK (0x1F << MIPSPLLCFG_6348_N2_SHIFT)
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#define MIPSPLLCFG_6348_N1_SHIFT 20
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#define MIPSPLLCFG_6348_N1_MASK (0x7 << MIPSPLLCFG_6348_N1_SHIFT)
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#define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8
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#define DMIPSPLLCFG_6358_M1_SHIFT 0
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#define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
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#define DMIPSPLLCFG_6358_N1_SHIFT 23
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#define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
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#define DMIPSPLLCFG_6358_N2_SHIFT 29
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#define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
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#define REG_BCM6362_MISC_STRAPBUS 0x1814
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#define STRAPBUS_6362_FCVO_SHIFT 1
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#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
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#define REG_BCM6368_DDR_DMIPSPLLCFG 0x12a0
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#define DMIPSPLLCFG_6368_P1_SHIFT 0
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#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
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#define DMIPSPLLCFG_6368_P2_SHIFT 4
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#define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
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#define DMIPSPLLCFG_6368_NDIV_SHIFT 16
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#define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
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#define REG_BCM6368_DDR_DMIPSPLLDIV 0x12a4
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#define DMIPSPLLDIV_6368_MDIV_SHIFT 0
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#define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
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#define REG_BCM63268_MISC_STRAPBUS 0x1814
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#define STRAPBUS_63268_FCVO_SHIFT 21
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#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
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#define REG_BCM6838_OTP_BRCMBITS0 0x440
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#define VIPER_6838_FREQ_SHIFT 18
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#define VIPER_6838_FREQ_MASK (0x7 << VIPER_6838_FREQ_SHIFT)
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struct bmips_cpu_priv;
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struct bmips_cpu_hw {
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int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
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ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
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int (*get_cpu_count)(struct bmips_cpu_priv *);
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};
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struct bmips_cpu_priv {
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void __iomem *regs;
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const struct bmips_cpu_hw *hw;
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};
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/* Specific CPU Ops */
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static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
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int size)
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{
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unsigned short cpu_id;
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unsigned char cpu_rev;
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u32 val;
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val = readl_be(priv->regs);
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cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
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cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
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snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
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return 0;
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}
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static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
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int size)
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{
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unsigned int cpu_id;
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unsigned char cpu_rev;
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u32 val;
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val = readl_be(priv->regs);
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cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
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cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
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snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
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return 0;
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}
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static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
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{
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return 333000000;
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}
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static ulong bcm6318_get_cpu_freq(struct bmips_cpu_priv *priv)
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{
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unsigned int mips_pll_fcvo;
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mips_pll_fcvo = readl_be(priv->regs + REG_BCM6318_STRAP_OVRDBUS);
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mips_pll_fcvo = (mips_pll_fcvo & OVRDBUS_6318_FREQ_MASK)
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>> OVRDBUS_6318_FREQ_SHIFT;
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switch (mips_pll_fcvo) {
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case 0:
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return 166000000;
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case 1:
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return 400000000;
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case 2:
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return 250000000;
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case 3:
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return 333000000;
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default:
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return 0;
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}
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}
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static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
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{
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unsigned int mips_pll_fcvo;
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mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS);
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mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
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>> STRAPBUS_6328_FCVO_SHIFT;
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switch (mips_pll_fcvo) {
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case 0x12:
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case 0x14:
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case 0x19:
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return 160000000;
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case 0x1c:
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return 192000000;
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case 0x13:
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case 0x15:
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return 200000000;
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case 0x1a:
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return 384000000;
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case 0x16:
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return 400000000;
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default:
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return 320000000;
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}
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}
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static ulong bcm6338_get_cpu_freq(struct bmips_cpu_priv *priv)
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{
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return 240000000;
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}
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static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
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{
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unsigned int tmp, n1, n2, m1;
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tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
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n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
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n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
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m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
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return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
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}
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static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
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{
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unsigned int tmp, n1, n2, m1;
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tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
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n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
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n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
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m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
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return (16 * 1000000 * n1 * n2) / m1;
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}
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static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv)
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{
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unsigned int mips_pll_fcvo;
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mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS);
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mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK)
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>> STRAPBUS_6362_FCVO_SHIFT;
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switch (mips_pll_fcvo) {
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case 0x03:
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case 0x0b:
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case 0x13:
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case 0x1b:
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return 240000000;
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case 0x04:
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case 0x0c:
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case 0x14:
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case 0x1c:
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return 160000000;
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case 0x05:
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case 0x0e:
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case 0x16:
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case 0x1e:
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case 0x1f:
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return 400000000;
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case 0x06:
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return 440000000;
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case 0x07:
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case 0x17:
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return 384000000;
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case 0x15:
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case 0x1d:
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return 200000000;
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default:
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return 320000000;
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}
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}
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static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv)
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{
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unsigned int tmp, p1, p2, ndiv, m1;
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tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLCFG);
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p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> DMIPSPLLCFG_6368_P1_SHIFT;
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p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> DMIPSPLLCFG_6368_P2_SHIFT;
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ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
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DMIPSPLLCFG_6368_NDIV_SHIFT;
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tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLDIV);
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m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> DMIPSPLLDIV_6368_MDIV_SHIFT;
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return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
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}
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static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
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{
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unsigned int mips_pll_fcvo;
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mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS);
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mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
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>> STRAPBUS_63268_FCVO_SHIFT;
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switch (mips_pll_fcvo) {
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case 0x3:
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case 0xe:
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return 320000000;
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case 0xa:
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return 333000000;
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case 0x2:
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case 0xb:
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case 0xf:
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return 400000000;
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default:
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return 0;
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}
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}
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static ulong bcm6838_get_cpu_freq(struct bmips_cpu_priv *priv)
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{
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unsigned int mips_viper_freq;
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mips_viper_freq = readl_be(priv->regs + REG_BCM6838_OTP_BRCMBITS0);
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mips_viper_freq = (mips_viper_freq & VIPER_6838_FREQ_MASK)
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>> VIPER_6838_FREQ_SHIFT;
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switch (mips_viper_freq) {
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case 0x0:
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return 600000000;
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case 0x1:
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return 400000000;
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case 0x2:
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return 240000000;
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default:
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return 0;
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}
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}
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static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
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{
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u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
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if (val & BCM6328_TP1_DISABLED)
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return 1;
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else
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return 2;
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}
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static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
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{
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return 1;
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}
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static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
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{
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return 2;
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}
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static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
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.get_cpu_desc = bmips_short_cpu_desc,
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.get_cpu_freq = bcm3380_get_cpu_freq,
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.get_cpu_count = bcm6358_get_cpu_count,
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};
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static const struct bmips_cpu_hw bmips_cpu_bcm6318 = {
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.get_cpu_desc = bmips_short_cpu_desc,
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.get_cpu_freq = bcm6318_get_cpu_freq,
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.get_cpu_count = bcm6345_get_cpu_count,
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};
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static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
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.get_cpu_desc = bmips_long_cpu_desc,
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.get_cpu_freq = bcm6328_get_cpu_freq,
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.get_cpu_count = bcm6328_get_cpu_count,
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};
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static const struct bmips_cpu_hw bmips_cpu_bcm6338 = {
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.get_cpu_desc = bmips_short_cpu_desc,
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.get_cpu_freq = bcm6338_get_cpu_freq,
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.get_cpu_count = bcm6345_get_cpu_count,
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};
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static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
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.get_cpu_desc = bmips_short_cpu_desc,
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.get_cpu_freq = bcm6348_get_cpu_freq,
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.get_cpu_count = bcm6345_get_cpu_count,
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};
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static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
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.get_cpu_desc = bmips_short_cpu_desc,
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.get_cpu_freq = bcm6358_get_cpu_freq,
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.get_cpu_count = bcm6358_get_cpu_count,
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};
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static const struct bmips_cpu_hw bmips_cpu_bcm6362 = {
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.get_cpu_desc = bmips_short_cpu_desc,
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.get_cpu_freq = bcm6362_get_cpu_freq,
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.get_cpu_count = bcm6358_get_cpu_count,
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};
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static const struct bmips_cpu_hw bmips_cpu_bcm6368 = {
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.get_cpu_desc = bmips_short_cpu_desc,
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.get_cpu_freq = bcm6368_get_cpu_freq,
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.get_cpu_count = bcm6358_get_cpu_count,
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};
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static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
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.get_cpu_desc = bmips_long_cpu_desc,
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.get_cpu_freq = bcm63268_get_cpu_freq,
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.get_cpu_count = bcm6358_get_cpu_count,
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};
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static const struct bmips_cpu_hw bmips_cpu_bcm6838 = {
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.get_cpu_desc = bmips_short_cpu_desc,
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.get_cpu_freq = bcm6838_get_cpu_freq,
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.get_cpu_count = bcm6358_get_cpu_count,
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};
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/* Generic CPU Ops */
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static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
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{
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struct bmips_cpu_priv *priv = dev_get_priv(dev);
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const struct bmips_cpu_hw *hw = priv->hw;
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return hw->get_cpu_desc(priv, buf, size);
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}
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static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info)
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{
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struct bmips_cpu_priv *priv = dev_get_priv(dev);
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const struct bmips_cpu_hw *hw = priv->hw;
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info->cpu_freq = hw->get_cpu_freq(priv);
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info->features = BIT(CPU_FEAT_L1_CACHE);
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info->features |= BIT(CPU_FEAT_MMU);
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info->features |= BIT(CPU_FEAT_DEVICE_ID);
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return 0;
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}
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static int bmips_cpu_get_count(struct udevice *dev)
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{
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struct bmips_cpu_priv *priv = dev_get_priv(dev);
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const struct bmips_cpu_hw *hw = priv->hw;
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return hw->get_cpu_count(priv);
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}
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static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size)
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{
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snprintf(buf, size, "Broadcom");
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return 0;
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}
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static const struct cpu_ops bmips_cpu_ops = {
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.get_desc = bmips_cpu_get_desc,
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.get_info = bmips_cpu_get_info,
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.get_count = bmips_cpu_get_count,
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.get_vendor = bmips_cpu_get_vendor,
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};
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/* BMIPS CPU driver */
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int bmips_cpu_bind(struct udevice *dev)
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{
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struct cpu_platdata *plat = dev_get_parent_platdata(dev);
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plat->cpu_id = dev_read_u32_default(dev, "reg", -1);
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plat->device_id = read_c0_prid();
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return 0;
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}
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int bmips_cpu_probe(struct udevice *dev)
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{
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struct bmips_cpu_priv *priv = dev_get_priv(dev);
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const struct bmips_cpu_hw *hw =
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(const struct bmips_cpu_hw *)dev_get_driver_data(dev);
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priv->regs = dev_remap_addr(dev_get_parent(dev));
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if (!priv->regs)
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return -EINVAL;
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priv->hw = hw;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id bmips_cpu_ids[] = {
|
|
{
|
|
.compatible = "brcm,bcm3380-cpu",
|
|
.data = (ulong)&bmips_cpu_bcm3380,
|
|
}, {
|
|
.compatible = "brcm,bcm6318-cpu",
|
|
.data = (ulong)&bmips_cpu_bcm6318,
|
|
}, {
|
|
.compatible = "brcm,bcm6328-cpu",
|
|
.data = (ulong)&bmips_cpu_bcm6328,
|
|
}, {
|
|
.compatible = "brcm,bcm6338-cpu",
|
|
.data = (ulong)&bmips_cpu_bcm6338,
|
|
}, {
|
|
.compatible = "brcm,bcm6348-cpu",
|
|
.data = (ulong)&bmips_cpu_bcm6348,
|
|
}, {
|
|
.compatible = "brcm,bcm6358-cpu",
|
|
.data = (ulong)&bmips_cpu_bcm6358,
|
|
}, {
|
|
.compatible = "brcm,bcm6362-cpu",
|
|
.data = (ulong)&bmips_cpu_bcm6362,
|
|
}, {
|
|
.compatible = "brcm,bcm6368-cpu",
|
|
.data = (ulong)&bmips_cpu_bcm6368,
|
|
}, {
|
|
.compatible = "brcm,bcm63268-cpu",
|
|
.data = (ulong)&bmips_cpu_bcm63268,
|
|
}, {
|
|
.compatible = "brcm,bcm6838-cpu",
|
|
.data = (ulong)&bmips_cpu_bcm6838,
|
|
},
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(bmips_cpu_drv) = {
|
|
.name = "bmips_cpu",
|
|
.id = UCLASS_CPU,
|
|
.of_match = bmips_cpu_ids,
|
|
.bind = bmips_cpu_bind,
|
|
.probe = bmips_cpu_probe,
|
|
.priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
|
|
.ops = &bmips_cpu_ops,
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
};
|
|
|
|
#ifdef CONFIG_DISPLAY_CPUINFO
|
|
int print_cpuinfo(void)
|
|
{
|
|
struct cpu_info cpu;
|
|
struct udevice *dev;
|
|
int err;
|
|
char desc[100];
|
|
|
|
err = uclass_get_device(UCLASS_CPU, 0, &dev);
|
|
if (err)
|
|
return 0;
|
|
|
|
err = cpu_get_info(dev, &cpu);
|
|
if (err)
|
|
return 0;
|
|
|
|
err = cpu_get_desc(dev, desc, sizeof(desc));
|
|
if (err)
|
|
return 0;
|
|
|
|
printf("Chip ID: %s, MIPS: ", desc);
|
|
print_freq(cpu.cpu_freq, "\n");
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|