upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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135 lines
3.3 KiB
135 lines
3.3 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015 Google, Inc
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*
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* (C) Copyright 2008-2014 Rockchip Electronics
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* Peter, Software Engineering, <superpeter.cai@gmail.com>.
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*/
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#include <common.h>
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#include <dm.h>
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#include <syscon.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <dm/pinctrl.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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enum {
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ROCKCHIP_GPIOS_PER_BANK = 32,
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};
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#define OFFSET_TO_BIT(bit) (1UL << (bit))
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struct rockchip_gpio_priv {
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struct rockchip_gpio_regs *regs;
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struct udevice *pinctrl;
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int bank;
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char name[2];
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};
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static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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struct rockchip_gpio_regs *regs = priv->regs;
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clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset));
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return 0;
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}
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static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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struct rockchip_gpio_regs *regs = priv->regs;
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int mask = OFFSET_TO_BIT(offset);
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clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
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setbits_le32(®s->swport_ddr, mask);
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return 0;
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}
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static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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struct rockchip_gpio_regs *regs = priv->regs;
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return readl(®s->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0;
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}
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static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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struct rockchip_gpio_regs *regs = priv->regs;
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int mask = OFFSET_TO_BIT(offset);
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clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
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return 0;
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}
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static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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#ifdef CONFIG_SPL_BUILD
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return -ENODATA;
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#else
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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struct rockchip_gpio_regs *regs = priv->regs;
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bool is_output;
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int ret;
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ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
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if (ret)
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return ret;
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is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset);
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return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
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#endif
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}
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static int rockchip_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct rockchip_gpio_priv *priv = dev_get_priv(dev);
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char *end;
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int ret;
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priv->regs = dev_read_addr_ptr(dev);
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ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
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if (ret)
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return ret;
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uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
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end = strrchr(dev->name, '@');
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priv->bank = trailing_strtoln(dev->name, end);
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priv->name[0] = 'A' + priv->bank;
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uc_priv->bank_name = priv->name;
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return 0;
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}
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static const struct dm_gpio_ops gpio_rockchip_ops = {
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.direction_input = rockchip_gpio_direction_input,
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.direction_output = rockchip_gpio_direction_output,
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.get_value = rockchip_gpio_get_value,
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.set_value = rockchip_gpio_set_value,
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.get_function = rockchip_gpio_get_function,
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};
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static const struct udevice_id rockchip_gpio_ids[] = {
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{ .compatible = "rockchip,gpio-bank" },
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{ }
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};
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U_BOOT_DRIVER(gpio_rockchip) = {
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.name = "gpio_rockchip",
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.id = UCLASS_GPIO,
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.of_match = rockchip_gpio_ids,
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.ops = &gpio_rockchip_ops,
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.priv_auto_alloc_size = sizeof(struct rockchip_gpio_priv),
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.probe = rockchip_gpio_probe,
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};
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