upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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453 lines
12 KiB
453 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Atmel PIO pinctrl driver
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*
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* Copyright (C) 2016 Atmel Corporation
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* Wenyou.Yang <wenyou.yang@atmel.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <asm/hardware.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <mach/at91_pio.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MAX_GPIO_BANKS 5
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#define MAX_NB_GPIO_PER_BANK 32
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#define MAX_PINMUX_ENTRIES 200
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struct at91_pinctrl_priv {
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struct at91_port *reg_base[MAX_GPIO_BANKS];
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u32 nbanks;
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};
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#define PULL_UP BIT(0)
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#define MULTI_DRIVE BIT(1)
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#define DEGLITCH BIT(2)
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#define PULL_DOWN BIT(3)
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#define DIS_SCHMIT BIT(4)
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#define DRIVE_STRENGTH_SHIFT 5
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#define DRIVE_STRENGTH_MASK 0x3
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#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
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#define OUTPUT BIT(7)
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#define OUTPUT_VAL_SHIFT 8
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#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
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#define DEBOUNCE BIT(16)
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#define DEBOUNCE_VAL_SHIFT 17
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#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
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/**
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* These defines will translated the dt binding settings to our internal
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* settings. They are not necessarily the same value as the register setting.
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* The actual drive strength current of low, medium and high must be looked up
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* from the corresponding device datasheet. This value is different for pins
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* that are even in the same banks. It is also dependent on VCC.
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* DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
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* strength when there is no dt config for it.
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*/
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#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
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#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
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#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
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#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
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enum at91_mux {
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AT91_MUX_GPIO = 0,
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AT91_MUX_PERIPH_A = 1,
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AT91_MUX_PERIPH_B = 2,
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AT91_MUX_PERIPH_C = 3,
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AT91_MUX_PERIPH_D = 4,
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};
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/**
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* struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
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* on new IP with support for periph C and D the way to mux in
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* periph A and B has changed
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* So provide the right callbacks
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* if not present means the IP does not support it
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* @mux_A_periph: assign the corresponding pin to the peripheral A function.
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* @mux_B_periph: assign the corresponding pin to the peripheral B function.
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* @mux_C_periph: assign the corresponding pin to the peripheral C function.
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* @mux_D_periph: assign the corresponding pin to the peripheral D function.
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* @set_deglitch: enable/disable the deglitch feature.
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* @set_debounce: enable/disable the debounce feature.
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* @set_pulldown: enable/disable the pulldown feature.
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* @disable_schmitt_trig: disable schmitt trigger
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*/
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struct at91_pinctrl_mux_ops {
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void (*mux_A_periph)(struct at91_port *pio, u32 mask);
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void (*mux_B_periph)(struct at91_port *pio, u32 mask);
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void (*mux_C_periph)(struct at91_port *pio, u32 mask);
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void (*mux_D_periph)(struct at91_port *pio, u32 mask);
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void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on);
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void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on,
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u32 div);
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void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on);
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void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
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void (*set_drivestrength)(struct at91_port *pio, u32 pin,
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u32 strength);
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};
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static u32 two_bit_pin_value_shift_amount(u32 pin)
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{
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/* return the shift value for a pin for "two bit" per pin registers,
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* i.e. drive strength */
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return 2 * ((pin >= MAX_NB_GPIO_PER_BANK/2)
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? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
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}
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static void at91_mux_disable_interrupt(struct at91_port *pio, u32 mask)
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{
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writel(mask, &pio->idr);
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}
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static void at91_mux_set_pullup(struct at91_port *pio, u32 mask, bool on)
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{
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if (on)
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writel(mask, &pio->mux.pio3.ppddr);
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writel(mask, (on ? &pio->puer : &pio->pudr));
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}
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static void at91_mux_set_output(struct at91_port *pio, unsigned mask,
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bool is_on, bool val)
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{
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writel(mask, (val ? &pio->sodr : &pio->codr));
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writel(mask, (is_on ? &pio->oer : &pio->odr));
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}
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static void at91_mux_set_multidrive(struct at91_port *pio, u32 mask, bool on)
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{
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writel(mask, (on ? &pio->mder : &pio->mddr));
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}
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static void at91_mux_set_A_periph(struct at91_port *pio, u32 mask)
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{
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writel(mask, &pio->mux.pio2.asr);
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}
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static void at91_mux_set_B_periph(struct at91_port *pio, u32 mask)
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{
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writel(mask, &pio->mux.pio2.bsr);
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}
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static void at91_mux_pio3_set_A_periph(struct at91_port *pio, u32 mask)
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{
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writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
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writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
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}
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static void at91_mux_pio3_set_B_periph(struct at91_port *pio, u32 mask)
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{
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writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
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writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
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}
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static void at91_mux_pio3_set_C_periph(struct at91_port *pio, u32 mask)
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{
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writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
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writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
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}
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static void at91_mux_pio3_set_D_periph(struct at91_port *pio, u32 mask)
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{
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writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
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writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
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}
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static void at91_mux_set_deglitch(struct at91_port *pio, u32 mask, bool is_on)
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{
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writel(mask, (is_on ? &pio->ifer : &pio->ifdr));
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}
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static void at91_mux_pio3_set_deglitch(struct at91_port *pio,
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u32 mask, bool is_on)
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{
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if (is_on)
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writel(mask, &pio->mux.pio3.ifscdr);
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at91_mux_set_deglitch(pio, mask, is_on);
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}
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static void at91_mux_pio3_set_debounce(struct at91_port *pio, u32 mask,
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bool is_on, u32 div)
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{
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if (is_on) {
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writel(mask, &pio->mux.pio3.ifscer);
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writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr);
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writel(mask, &pio->ifer);
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} else {
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writel(mask, &pio->mux.pio3.ifscdr);
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}
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}
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static void at91_mux_pio3_set_pulldown(struct at91_port *pio,
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u32 mask, bool is_on)
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{
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if (is_on)
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writel(mask, &pio->pudr);
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writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr));
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}
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static void at91_mux_pio3_disable_schmitt_trig(struct at91_port *pio,
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u32 mask)
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{
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writel(readl(&pio->schmitt) | mask, &pio->schmitt);
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}
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static void set_drive_strength(void *reg, u32 pin, u32 strength)
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{
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u32 shift = two_bit_pin_value_shift_amount(pin);
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clrsetbits_le32(reg, DRIVE_STRENGTH_MASK << shift, strength << shift);
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}
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static void at91_mux_sama5d3_set_drivestrength(struct at91_port *pio,
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u32 pin, u32 setting)
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{
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void *reg;
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reg = &pio->driver12;
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if (pin >= MAX_NB_GPIO_PER_BANK / 2)
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reg = &pio->driver2;
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/* do nothing if setting is zero */
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if (!setting)
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return;
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/* strength is 1 to 1 with setting for SAMA5 */
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set_drive_strength(reg, pin, setting);
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}
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static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
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u32 pin, u32 setting)
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{
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void *reg;
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reg = &pio->driver1;
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if (pin >= MAX_NB_GPIO_PER_BANK / 2)
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reg = &pio->driver12;
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/* do nothing if setting is zero */
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if (!setting)
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return;
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/* strength is inverse on SAM9x5s with our defines
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* 0 = hi, 1 = med, 2 = low, 3 = rsvd */
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setting = DRIVE_STRENGTH_HI - setting;
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set_drive_strength(reg, pin, setting);
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}
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static struct at91_pinctrl_mux_ops at91rm9200_ops = {
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.mux_A_periph = at91_mux_set_A_periph,
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.mux_B_periph = at91_mux_set_B_periph,
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.set_deglitch = at91_mux_set_deglitch,
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};
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static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
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.mux_A_periph = at91_mux_pio3_set_A_periph,
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.mux_B_periph = at91_mux_pio3_set_B_periph,
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.mux_C_periph = at91_mux_pio3_set_C_periph,
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.mux_D_periph = at91_mux_pio3_set_D_periph,
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.set_deglitch = at91_mux_pio3_set_deglitch,
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.set_debounce = at91_mux_pio3_set_debounce,
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.set_pulldown = at91_mux_pio3_set_pulldown,
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.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
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.set_drivestrength = at91_mux_sam9x5_set_drivestrength,
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};
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static struct at91_pinctrl_mux_ops sama5d3_ops = {
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.mux_A_periph = at91_mux_pio3_set_A_periph,
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.mux_B_periph = at91_mux_pio3_set_B_periph,
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.mux_C_periph = at91_mux_pio3_set_C_periph,
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.mux_D_periph = at91_mux_pio3_set_D_periph,
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.set_deglitch = at91_mux_pio3_set_deglitch,
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.set_debounce = at91_mux_pio3_set_debounce,
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.set_pulldown = at91_mux_pio3_set_pulldown,
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.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
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.set_drivestrength = at91_mux_sama5d3_set_drivestrength,
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};
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static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
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{
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writel(mask, &pio->pdr);
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}
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static void at91_mux_gpio_enable(struct at91_port *pio, u32 mask, bool input)
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{
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writel(mask, &pio->per);
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writel(mask, (input ? &pio->odr : &pio->oer));
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}
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static int at91_pmx_set(struct at91_pinctrl_mux_ops *ops,
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struct at91_port *pio, u32 mask, enum at91_mux mux)
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{
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at91_mux_disable_interrupt(pio, mask);
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switch (mux) {
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case AT91_MUX_GPIO:
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at91_mux_gpio_enable(pio, mask, 1);
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break;
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case AT91_MUX_PERIPH_A:
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ops->mux_A_periph(pio, mask);
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break;
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case AT91_MUX_PERIPH_B:
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ops->mux_B_periph(pio, mask);
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break;
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case AT91_MUX_PERIPH_C:
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if (!ops->mux_C_periph)
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return -EINVAL;
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ops->mux_C_periph(pio, mask);
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break;
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case AT91_MUX_PERIPH_D:
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if (!ops->mux_D_periph)
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return -EINVAL;
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ops->mux_D_periph(pio, mask);
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break;
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}
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if (mux)
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at91_mux_gpio_disable(pio, mask);
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return 0;
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}
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static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
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struct at91_port *pio, u32 pin, u32 config)
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{
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u32 mask = BIT(pin);
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if ((config & PULL_UP) && (config & PULL_DOWN))
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return -EINVAL;
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at91_mux_set_output(pio, mask, config & OUTPUT,
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(config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
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at91_mux_set_pullup(pio, mask, config & PULL_UP);
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at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
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if (ops->set_deglitch)
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ops->set_deglitch(pio, mask, config & DEGLITCH);
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if (ops->set_debounce)
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ops->set_debounce(pio, mask, config & DEBOUNCE,
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(config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
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if (ops->set_pulldown)
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ops->set_pulldown(pio, mask, config & PULL_DOWN);
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if (ops->disable_schmitt_trig && config & DIS_SCHMIT)
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ops->disable_schmitt_trig(pio, mask);
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if (ops->set_drivestrength)
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ops->set_drivestrength(pio, pin,
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(config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT);
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return 0;
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}
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static int at91_pin_check_config(struct udevice *dev, u32 bank, u32 pin)
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{
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struct at91_pinctrl_priv *priv = dev_get_priv(dev);
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if (bank >= priv->nbanks) {
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debug("pin conf bank %d >= nbanks %d\n", bank, priv->nbanks);
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return -EINVAL;
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}
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if (pin >= MAX_NB_GPIO_PER_BANK) {
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debug("pin conf pin %d >= %d\n", pin, MAX_NB_GPIO_PER_BANK);
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return -EINVAL;
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}
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return 0;
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}
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static int at91_pinctrl_set_state(struct udevice *dev, struct udevice *config)
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{
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struct at91_pinctrl_priv *priv = dev_get_priv(dev);
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(config);
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u32 cells[MAX_PINMUX_ENTRIES];
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const u32 *list = cells;
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u32 bank, pin;
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u32 conf, mask, count, i;
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int size;
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int ret;
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enum at91_mux mux;
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struct at91_port *pio;
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struct at91_pinctrl_mux_ops *ops =
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(struct at91_pinctrl_mux_ops *)dev_get_driver_data(dev);
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/*
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* the binding format is atmel,pins = <bank pin mux CONFIG ...>,
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* do sanity check and calculate pins number
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*/
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size = fdtdec_get_int_array_count(blob, node, "atmel,pins",
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cells, ARRAY_SIZE(cells));
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/* we do not check return since it's safe node passed down */
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count = size >> 2;
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if (!count)
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return -EINVAL;
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for (i = 0; i < count; i++) {
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bank = *list++;
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pin = *list++;
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mux = *list++;
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conf = *list++;
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ret = at91_pin_check_config(dev, bank, pin);
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if (ret)
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return ret;
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pio = priv->reg_base[bank];
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mask = BIT(pin);
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ret = at91_pmx_set(ops, pio, mask, mux);
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if (ret)
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return ret;
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ret = at91_pinconf_set(ops, pio, pin, conf);
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if (ret)
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return ret;
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}
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return 0;
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}
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const struct pinctrl_ops at91_pinctrl_ops = {
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.set_state = at91_pinctrl_set_state,
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};
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static int at91_pinctrl_probe(struct udevice *dev)
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{
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struct at91_pinctrl_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr_base;
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int index;
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for (index = 0; index < MAX_GPIO_BANKS; index++) {
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addr_base = devfdt_get_addr_index(dev, index);
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if (addr_base == FDT_ADDR_T_NONE)
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break;
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priv->reg_base[index] = (struct at91_port *)addr_base;
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}
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priv->nbanks = index;
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return 0;
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}
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static const struct udevice_id at91_pinctrl_match[] = {
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{ .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops },
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{ .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops },
|
|
{ .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops },
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(at91_pinctrl) = {
|
|
.name = "pinctrl_at91",
|
|
.id = UCLASS_PINCTRL,
|
|
.of_match = at91_pinctrl_match,
|
|
.probe = at91_pinctrl_probe,
|
|
.priv_auto_alloc_size = sizeof(struct at91_pinctrl_priv),
|
|
.ops = &at91_pinctrl_ops,
|
|
};
|
|
|