upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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224 lines
6.8 KiB
224 lines
6.8 KiB
/*
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* Configuration settings for the Gumstix Overo board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define CONFIG_NAND
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#include <configs/ti_omap3_common.h>
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/* Display CPU and Board information */
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* call misc_init_r */
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#define CONFIG_MISC_INIT_R
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/* pass the revision tag */
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#define CONFIG_REVISION_TAG
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/* override size of malloc() pool */
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#undef CONFIG_SYS_MALLOC_LEN
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
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/* Shift 128 << 15 provides 4 MiB heap to support UBI commands.
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* Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 15))
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/* I2C Support */
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#define CONFIG_SYS_I2C_OMAP34XX
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/* TWL4030 LED */
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#define CONFIG_TWL4030_LED
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/* Initialize GPIOs by default */
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#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */
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#define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */
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#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */
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#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO Bank 5 */
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#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */
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/* commands to include */
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#define CONFIG_CMD_CACHE
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#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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#undef CONFIG_CMD_IMI /* iminfo */
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#undef CONFIG_CMD_NFS /* NFS support */
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#ifdef CONFIG_NAND
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#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
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#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
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#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
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#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
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#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
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/* NAND block size is 128 KiB. Synchronize these values with
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* overo_nand_partitions in mach-omap2/board-overo.c in Linux:
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* xloader 4 * NAND_BLOCK_SIZE = 512 KiB
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* uboot 14 * NAND_BLOCK_SIZE = 1792 KiB
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* uboot environtment 2 * NAND_BLOCK_SIZE = 256 KiB
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* linux 64 * NAND_BLOCK_SIZE = 8 MiB
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* rootfs remainder
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*/
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#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
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"512k(xloader)," \
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"1792k(u-boot)," \
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"256k(environ)," \
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"8m(linux)," \
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"-(rootfs)"
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#else /* CONFIG_NAND */
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#define MTDPARTS_DEFAULT
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#endif /* CONFIG_NAND */
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/* Board NAND Info. */
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#define CONFIG_SYS_NAND_QUIET_TEST
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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/* Environment information */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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DEFAULT_LINUX_BOOT_ENV \
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"fdtfile=overo.dtb\0" \
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"bootdir=/boot\0" \
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"bootfile=zImage\0" \
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"usbtty=cdc_acm\0" \
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"console=ttyO2,115200n8\0" \
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"mpurate=auto\0" \
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"optargs=\0" \
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"vram=12M\0" \
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"dvimode=1024x768MR-16@60\0" \
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"defaultdisplay=dvi\0" \
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"mmcdev=0\0" \
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"mmcroot=/dev/mmcblk0p2 rw\0" \
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"mmcrootfstype=ext3 rootwait\0" \
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"nandroot=ubi0:rootfs ubi.mtd=4\0" \
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"nandrootfstype=ubifs\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"${optargs} " \
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"mpurate=${mpurate} " \
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype}\0" \
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"nandargs=setenv bootargs console=${console} " \
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"${optargs} " \
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"mpurate=${mpurate} " \
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"vram=${vram} " \
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"omapfb.mode=dvi:${dvimode} " \
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"omapdss.def_disp=${defaultdisplay} " \
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"root=${nandroot} " \
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"rootfstype=${nandrootfstype}\0" \
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"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo Running boot script from mmc ...; " \
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"source ${loadaddr}\0" \
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"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
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"importbootenv=echo Importing environment from mmc ...; " \
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"env import -t ${loadaddr} ${filesize}\0" \
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"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
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"mmcboot=echo Booting from mmc...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
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"loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
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"mmcbootfdt=echo Booting with DT from mmc ...; " \
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"run mmcargs; " \
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"bootz ${loadaddr} - ${fdtaddr}\0" \
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"nandboot=echo Booting from nand ...; " \
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"run nandargs; " \
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"nand read ${loadaddr} linux; " \
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"bootm ${loadaddr}\0" \
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"fi;" \
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"if run loadbootenv; then " \
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"echo Loaded environment from ${bootenv};" \
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"run importbootenv;" \
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"fi;" \
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"if test -n $uenvcmd; then " \
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"echo Running uenvcmd ...;" \
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"run uenvcmd;" \
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"fi;" \
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"if run loaduimage; then " \
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"run mmcboot;" \
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"fi;" \
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"if run loadzimage; then " \
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"if test -n $fdtfile; then " \
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"if run loadfdt; then " \
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"run mmcbootfdt;" \
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"fi;" \
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"fi;" \
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"fi;" \
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"fi;" \
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"run nandboot; " \
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/*
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* Miscellaneous configurable options
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*/
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#undef CONFIG_SYS_PROMPT
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#define CONFIG_SYS_PROMPT "Overo # "
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
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0x01F00000) /* 31MB */
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/* FLASH and environment organization */
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/* Configure the PISMO */
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
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#if defined(CONFIG_NAND)
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#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
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#endif
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
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#define CONFIG_ENV_IS_IN_NAND
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#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
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#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
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/* Configure SMSC9211 ethernet */
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_32_BIT
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#define CONFIG_SMC911X_BASE 0x2C000000
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#endif /* (CONFIG_CMD_NET) */
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/* Initial RAM setup */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_CACHELINE_SIZE 64
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/* NAND boot config */
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#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#endif /* __CONFIG_H */
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