upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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284 lines
7.2 KiB
284 lines
7.2 KiB
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* cpci5200.c - main board support/init for the esd cpci5200.
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#include <command.h>
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#include <netdev.h>
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#include "mt46v16m16-75.h"
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void init_ata_reset(void);
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static void sdram_start(int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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*(vu_long *) MPC5XXX_SDRAM_CTRL =
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SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* precharge all banks */
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*(vu_long *) MPC5XXX_SDRAM_CTRL =
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SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* set mode register: extended mode */
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*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
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__asm__ volatile ("sync");
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/* set mode register: reset DLL */
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*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
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__asm__ volatile ("sync");
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/* precharge all banks */
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*(vu_long *) MPC5XXX_SDRAM_CTRL =
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SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* auto refresh */
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*(vu_long *) MPC5XXX_SDRAM_CTRL =
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SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* set mode register */
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*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
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__asm__ volatile ("sync");
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/* normal operation */
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*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
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__asm__ volatile ("sync");
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}
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
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* is something else than 0x00000000.
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*/
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phys_size_t initdram(int board_type)
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{
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ulong dramsize = 0;
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ulong test1, test2;
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/* setup SDRAM chip selects */
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*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
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__asm__ volatile ("sync");
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/* setup config registers */
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*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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__asm__ volatile ("sync");
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/* set tap delay */
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*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
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__asm__ volatile ("sync");
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20)) {
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dramsize = 0;
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}
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
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0x13 + __builtin_ffs(dramsize >> 20) - 1;
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/* let SDRAM CS1 start right after CS0 */
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
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} else {
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#if 0
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*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
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/* let SDRAM CS1 start right after CS0 */
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
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#else
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*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
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0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
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/* let SDRAM CS1 start right after CS0 */
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
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#endif
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}
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#if 0
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/* find RAM size using SDRAM CS1 only */
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sdram_start(0);
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get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
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sdram_start(1);
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get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
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sdram_start(0);
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#endif
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/* set SDRAM CS1 size according to the amount of RAM found */
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
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init_ata_reset();
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return (dramsize);
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}
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int checkboard(void)
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{
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puts("Board: esd CPCI5200 (cpci5200)\n");
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return 0;
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}
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void flash_preinit(void)
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{
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/*
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* Now, when we are in RAM, enable flash write
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* access for detection process.
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* Note that CS_BOOT cannot be cleared when
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* executing in flash.
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*/
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*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
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}
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void flash_afterinit(ulong size)
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{
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if (size == 0x02000000) {
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/* adjust mapping */
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*(vu_long *) MPC5XXX_BOOTCS_START =
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*(vu_long *) MPC5XXX_CS0_START =
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START_REG(CONFIG_SYS_BOOTCS_START | size);
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*(vu_long *) MPC5XXX_BOOTCS_STOP =
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*(vu_long *) MPC5XXX_CS0_STOP =
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STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
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}
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}
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void) {
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pci_mpc5xxx_init(&hose);
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}
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#endif
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#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
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void init_ide_reset(void)
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{
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debug("init_ide_reset\n");
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/* Configure PSC1_4 as GPIO output for ATA reset */
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
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}
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void ide_set_reset(int idereset)
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{
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debug("ide_reset(%d)\n", idereset);
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if (idereset) {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
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} else {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
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}
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}
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#endif
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#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
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#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
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#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
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#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
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#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
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#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
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#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
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#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
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#define GPIO_WU6 0x40000000UL
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#define GPIO_USB0 0x00010000UL
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#define GPIO_USB9 0x08000000UL
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#define GPIO_USB9S 0x00080000UL
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void init_ata_reset(void)
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{
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debug("init_ata_reset\n");
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/* Configure GPIO_WU6 as GPIO output for ATA reset */
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
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__asm__ volatile ("sync");
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*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
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*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
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*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
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__asm__ volatile ("sync");
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*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
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*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
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__asm__ volatile ("sync");
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if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
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*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
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__asm__ volatile ("sync");
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}
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned int addr;
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unsigned int size;
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int i;
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volatile unsigned long *ptr;
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addr = simple_strtol(argv[1], NULL, 16);
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size = simple_strtol(argv[2], NULL, 16);
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printf("\nWriting at addr %08x, size %08x.\n", addr, size);
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while (1) {
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ptr = (volatile unsigned long *)addr;
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for (i = 0; i < (size >> 2); i++) {
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*ptr++ = i;
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}
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/* Abort if ctrl-c was pressed */
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if (ctrlc()) {
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puts("\nAbort\n");
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return 0;
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}
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putc('.');
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}
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return 0;
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}
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U_BOOT_CMD(writepci, 3, 1, do_writepci,
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"Write some data to pcibus",
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"<addr> <size>\n"
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""
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);
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