upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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474 lines
11 KiB
474 lines
11 KiB
/*
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* armboot - Startup Code for XScale
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*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
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* Copyright (C) 2001 Alex Züpke <azu@sysgo.de>
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* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
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* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
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* Copyright (C) 2003 Kai-Uwe Bloehm <kai-uwe.bloem@auerswald.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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.globl _start
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_start: b reset
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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.balignl 16,0xdeadbeef
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/*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* - relocate armboot to ram
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* - setup stack
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* - jump to second stage
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*/
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/*
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* CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
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*/
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_TEXT_BASE:
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.word TEXT_BASE
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.globl _armboot_start
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_armboot_start:
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.word _start
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/*
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* Note: _armboot_end_data and _armboot_end are defined
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* by the (board-dependent) linker script.
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* _armboot_end_data is the first usable FLASH address after armboot
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*/
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.globl _armboot_end_data
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_armboot_end_data:
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.word armboot_end_data
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.globl _armboot_end
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_armboot_end:
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.word armboot_end
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/*
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* This is defined in the board specific linker script
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*/
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.globl _bss_start
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_bss_start:
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.word bss_start
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.globl _bss_end
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_bss_end:
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.word bss_end
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/*
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* _armboot_real_end is the first usable RAM address behind armboot
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* and the various stacks
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*/
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.globl _armboot_real_end
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_armboot_real_end:
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.word 0x0badc0de
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/*
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* We relocate uboot to this address (end of RAM - 128 KiB)
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*/
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.globl _uboot_reloc
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_uboot_reloc:
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.word TEXT_BASE
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif
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/****************************************************************************/
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/* */
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/* the actual reset code */
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/* */
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/****************************************************************************/
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reset:
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mrs r0,cpsr /* set the cpu to SVC32 mode */
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bic r0,r0,#0x1f /* (superviser mode, M=10011) */
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orr r0,r0,#0x13
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msr cpsr,r0
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bl cpu_init_crit /* we do sys-critical inits */
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relocate: /* relocate U-Boot to RAM */
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adr r0, _start /* r0 <- current position of code */
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ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
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cmp r0, r1 /* don't reloc during debug */
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beq stack_setup
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ldr r2, _armboot_start
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ldr r3, _armboot_end
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sub r2, r3, r2 /* r2 <- size of armboot */
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add r2, r0, r2 /* r2 <- source end address */
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copy_loop:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end addreee [r2] */
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ble copy_loop
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/* Set up the stack */
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stack_setup:
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ldr r0, _uboot_reloc /* upper 128 KiB: relocated uboot */
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sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
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/* FIXME: bdinfo should be here */
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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clear_bss:
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ldr r0, _bss_start /* find start of bss segment */
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add r0, r0, #4 /* start at first byte of bss */
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ldr r1, _bss_end /* stop here */
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mov r2, #0x00000000 /* clear */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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bne clbss_l
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ldr pc, _start_armboot
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_start_armboot: .word start_armboot
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/****************************************************************************/
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/* */
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/* CPU_init_critical registers */
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/* */
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/* - setup important registers */
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/* - setup memory timing */
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/* */
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/****************************************************************************/
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/* Interrupt-Controller base address */
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IC_BASE: .word 0x40d00000
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#define ICMR 0x04
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/* Reset-Controller */
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RST_BASE: .word 0x40f00030
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#define RCSR 0x00
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/* Operating System Timer */
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OSTIMER_BASE: .word 0x40a00000
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#define OSMR3 0x0C
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#define OSCR 0x10
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#define OWER 0x18
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#define OIER 0x1C
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/* Clock Manager Registers */
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CC_BASE: .word 0x41300000
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#define CCCR 0x00
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cpuspeed: .word CFG_CPUSPEED
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/* RS: ??? */
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.macro CPWAIT
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mrc p15,0,r0,c2,c0,0
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mov r0,r0
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sub pc,pc,#4
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.endm
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cpu_init_crit:
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/* mask all IRQs */
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ldr r0, IC_BASE
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mov r1, #0x00
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str r1, [r0, #ICMR]
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#if defined(CFG_CPUSPEED)
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/* set clock speed */
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ldr r0, CC_BASE
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ldr r1, cpuspeed
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str r1, [r0, #CCCR]
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mov r0, #2
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mcr p14, 0, r0, c6, c0, 0
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setspeed_done:
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#endif
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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* find a memsetup.S in your board directory.
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*/
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mov ip, lr
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bl memsetup
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mov lr, ip
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/* Memory interfaces are working. Disable MMU and enable I-cache. */
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ldr r0, =0x2001 /* enable access to all coproc. */
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mcr p15, 0, r0, c15, c1, 0
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CPWAIT
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mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
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CPWAIT
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mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
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CPWAIT
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mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
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CPWAIT
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/* Enable the Icache */
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/*
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x1800
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT
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*/
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mov pc, lr
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/****************************************************************************/
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/* */
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/* Interrupt handling */
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/* */
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/****************************************************************************/
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/* IRQ stack frame */
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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/* use bad_save_user_regs for abort/prefetch/undef/swi ... */
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} /* Calling r0-r12 */
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add r8, sp, #S_PC
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ldr r2, _armboot_end
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add r2, r2, #CONFIG_STACKSIZE
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sub r2, r2, #8
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ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
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add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
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mov r0, sp
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.endm
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/* use irq_save_user_regs / irq_restore_user_regs for */
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/* IRQ/FIQ handling */
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} /* Calling r0-r12 */
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add r8, sp, #S_PC
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stmdb r8, {sp, lr}^ /* Calling SP, LR */
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str lr, [r8, #0] /* Save calling PC */
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mrs r6, spsr
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str r6, [r8, #4] /* Save CPSR */
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str r0, [r8, #8] /* Save OLD_R0 */
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mov r0, sp
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.endm
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0
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ldr lr, [sp, #S_PC] @ Get PC
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add sp, sp, #S_FRAME_SIZE
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subs pc, lr, #4 @ return & move spsr_svc into cpsr
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.endm
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.macro get_bad_stack
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ldr r13, _armboot_end @ setup our mode stack
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add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
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sub r13, r13, #8
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str lr, [r13] @ save caller lr / spsr
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mrs lr, spsr
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str lr, [r13, #4]
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mov r13, #MODE_SVC @ prepare SVC-Mode
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msr spsr_c, r13
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mov lr, pc
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movs pc, lr
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.endm
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START
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.endm
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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/****************************************************************************/
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/* */
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/* exception handlers */
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/* */
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/****************************************************************************/
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack
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bad_save_user_regs
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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.align 5
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data_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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.align 5
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not_used:
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get_bad_stack
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bad_save_user_regs
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bl do_not_used
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#ifdef CONFIG_USE_IRQ
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.align 5
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irq:
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get_irq_stack
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irq_save_user_regs
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bl do_irq
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irq_restore_user_regs
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.align 5
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fiq:
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get_fiq_stack
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irq_save_user_regs /* someone ought to write a more */
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bl do_fiq /* effiction fiq_save_user_regs */
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irq_restore_user_regs
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#else
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.align 5
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irq:
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get_bad_stack
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bad_save_user_regs
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bl do_irq
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.align 5
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fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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#endif
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/****************************************************************************/
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/* */
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/* Reset function: the PXA250 doesn't have a reset function, so we have to */
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/* perform a watchdog timeout for a soft reset. */
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/* */
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/****************************************************************************/
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.align 5
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.globl reset_cpu
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/* FIXME: this code is PXA250 specific. How is this handled on */
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/* other XScale processors? */
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reset_cpu:
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/* We set OWE:WME (watchdog enable) and wait until timeout happens */
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ldr r0, OSTIMER_BASE
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ldr r1, [r0, #OWER]
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orr r1, r1, #0x0001 /* bit0: WME */
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str r1, [r0, #OWER]
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/* OS timer does only wrap every 1165 seconds, so we have to set */
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/* the match register as well. */
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ldr r1, [r0, #OSCR] /* read OS timer */
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add r1, r1, #0x800 /* let OSMR3 match after */
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add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
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str r1, [r0, #OSMR3]
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reset_endless:
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b reset_endless
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