upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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213 lines
4.6 KiB
213 lines
4.6 KiB
/*
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* U-boot - cpu.c CPU specific functions
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*
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* Copyright (c) 2005-2007 Analog Devices Inc.
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/blackfin.h>
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#include <command.h>
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#include <asm/entry.h>
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#include <asm/cplb.h>
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#include <asm/io.h>
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#define CACHE_ON 1
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#define CACHE_OFF 0
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extern unsigned int icplb_table[page_descriptor_table_size][2];
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extern unsigned int dcplb_table[page_descriptor_table_size][2];
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int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
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);
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return 0;
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}
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/* These functions are just used to satisfy the linker */
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int cpu_init(void)
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{
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return 0;
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}
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int cleanup_before_linux(void)
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{
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return 0;
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}
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void icache_enable(void)
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{
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unsigned int *I0, *I1;
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int i, j = 0;
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/* Before enable icache, disable it first */
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icache_disable();
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I0 = (unsigned int *)ICPLB_ADDR0;
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I1 = (unsigned int *)ICPLB_DATA0;
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/* make sure the locked ones go in first */
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for (i = 0; i < page_descriptor_table_size; i++) {
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if (CPLB_LOCK & icplb_table[i][1]) {
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debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
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icplb_table[i][0], icplb_table[i][1]);
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*I0++ = icplb_table[i][0];
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*I1++ = icplb_table[i][1];
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j++;
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}
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}
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for (i = 0; i < page_descriptor_table_size; i++) {
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if (!(CPLB_LOCK & icplb_table[i][1])) {
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debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
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icplb_table[i][0], icplb_table[i][1]);
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*I0++ = icplb_table[i][0];
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*I1++ = icplb_table[i][1];
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j++;
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if (j == 16) {
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break;
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}
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}
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}
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/* Fill the rest with invalid entry */
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if (j <= 15) {
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for (; j < 16; j++) {
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debug("filling %i with 0", j);
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*I1++ = 0x0;
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}
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}
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SSYNC();
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asm(" .align 8; ");
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*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
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SSYNC();
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}
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void icache_disable(void)
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{
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SSYNC();
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asm(" .align 8; ");
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*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
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SSYNC();
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}
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int icache_status(void)
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{
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unsigned int value;
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value = *(unsigned int *)IMEM_CONTROL;
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if (value & (IMC | ENICPLB))
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return CACHE_ON;
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else
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return CACHE_OFF;
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}
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void dcache_enable(void)
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{
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unsigned int *I0, *I1;
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unsigned int temp;
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int i, j = 0;
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/* Before enable dcache, disable it first */
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dcache_disable();
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I0 = (unsigned int *)DCPLB_ADDR0;
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I1 = (unsigned int *)DCPLB_DATA0;
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/* make sure the locked ones go in first */
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for (i = 0; i < page_descriptor_table_size; i++) {
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if (CPLB_LOCK & dcplb_table[i][1]) {
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debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
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dcplb_table[i][0], dcplb_table[i][1]);
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*I0++ = dcplb_table[i][0];
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*I1++ = dcplb_table[i][1];
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j++;
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} else {
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debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
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dcplb_table[i][0], dcplb_table[i][1]);
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}
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}
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for (i = 0; i < page_descriptor_table_size; i++) {
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if (!(CPLB_LOCK & dcplb_table[i][1])) {
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debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
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dcplb_table[i][0], dcplb_table[i][1]);
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*I0++ = dcplb_table[i][0];
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*I1++ = dcplb_table[i][1];
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j++;
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if (j == 16) {
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break;
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}
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}
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}
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/* Fill the rest with invalid entry */
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if (j <= 15) {
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for (; j < 16; j++) {
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debug("filling %i with 0", j);
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*I1++ = 0x0;
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}
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}
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temp = *(unsigned int *)DMEM_CONTROL;
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SSYNC();
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asm(" .align 8; ");
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*(unsigned int *)DMEM_CONTROL =
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ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
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SSYNC();
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}
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void dcache_disable(void)
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{
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unsigned int *I0, *I1;
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int i;
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SSYNC();
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asm(" .align 8; ");
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*(unsigned int *)DMEM_CONTROL &=
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~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
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SSYNC();
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/* after disable dcache,
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* clear it so we don't confuse the next application
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*/
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I0 = (unsigned int *)DCPLB_ADDR0;
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I1 = (unsigned int *)DCPLB_DATA0;
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for (i = 0; i < 16; i++) {
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*I0++ = 0x0;
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*I1++ = 0x0;
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}
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}
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int dcache_status(void)
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{
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unsigned int value;
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value = *(unsigned int *)DMEM_CONTROL;
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if (value & (ENDCPLB))
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return CACHE_ON;
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else
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return CACHE_OFF;
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}
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