upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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295 lines
7.9 KiB
295 lines
7.9 KiB
/*
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* U-boot - Configuration file for BF537 STAMP board
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*/
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#ifndef __CONFIG_BF537_STAMP_H__
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#define __CONFIG_BF537_STAMP_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf537-0.2
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 25000000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 20
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 4
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_ADD_WDTH 10
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#define CONFIG_MEM_SIZE 64
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#define CONFIG_EBIU_SDRRC_VAL 0x306
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#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
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#define CONFIG_EBIU_AMGCTL_VAL 0xFF
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#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
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/*
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* Network Settings
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*/
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#ifndef __ADSPBF534__
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#define ADI_CMDS_NETWORK 1
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#define CONFIG_BFIN_MAC
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#define CONFIG_NETCONSOLE 1
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_HOSTNAME bf537-stamp
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/* Uncomment next line to use fixed MAC address */
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/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
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/*
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* Flash Settings
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*/
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x20000000
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
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#define CONFIG_SYS_MAX_FLASH_SECT 71
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/*
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* SPI Settings
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*/
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#define CONFIG_BFIN_SPI
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_ATMEL
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SPI_FLASH_WINBOND
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/*
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* Env Storage Settings
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*/
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x10000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OFFSET 0x4000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#endif
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
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#define ENV_IS_EMBEDDED
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#else
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#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
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#endif
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#ifdef ENV_IS_EMBEDDED
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/* WARNING - the following is hand-optimized to fit within
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* the sector before the environment sector. If it throws
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* an error during compilation remove an object here to get
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* it linked after the configuration sector.
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*/
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# define LDS_BOARD_TEXT \
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arch/blackfin/cpu/traps.o (.text .text.*); \
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arch/blackfin/cpu/interrupt.o (.text .text.*); \
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arch/blackfin/cpu/serial.o (.text .text.*); \
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common/dlmalloc.o (.text .text.*); \
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lib/crc32.o (.text .text.*); \
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. = DEFINED(env_offset) ? env_offset : .; \
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common/env_embedded.o (.text .text.*);
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#endif
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/*
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* I2C Settings
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*/
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#define CONFIG_BFIN_TWI_I2C 1
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 50000
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#define CONFIG_SYS_I2C_SLAVE 0
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/*
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* SPI_MMC Settings
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*/
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#define CONFIG_MMC
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#define CONFIG_SPI_MMC
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/*
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* NAND Settings
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*/
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/* #define CONFIG_NAND_PLAT */
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#define CONFIG_SYS_NAND_BASE 0x20212000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
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#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
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#define BFIN_NAND_READY PF3
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#define BFIN_NAND_WRITE(addr, cmd) \
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do { \
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bfin_write8(addr, cmd); \
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SSYNC(); \
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} while (0)
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#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
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#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
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#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTFIO() & BFIN_NAND_READY)
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#define NAND_PLAT_INIT() \
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do { \
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bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \
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bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \
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bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \
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} while (0)
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/*
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* CF-CARD IDE-HDD Support
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*/
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/*
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* Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
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* Strange address mapping Blackfin A13 connects to CF_A0
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*/
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/* #define CONFIG_BFIN_TRUE_IDE */
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/*
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* Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
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* This should be the preferred mode
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*/
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/* #define CONFIG_BFIN_CF_IDE */
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/*
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* Add IDE Disk Drive (HDD) support
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* See example interface here:
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* http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
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*/
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/* #define CONFIG_BFIN_HDD_IDE */
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#if defined(CONFIG_BFIN_CF_IDE) || \
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defined(CONFIG_BFIN_HDD_IDE) || \
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defined(CONFIG_BFIN_TRUE_IDE)
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# define CONFIG_BFIN_IDE 1
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# define CONFIG_CMD_IDE
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#endif
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#if defined(CONFIG_BFIN_IDE)
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#define CONFIG_DOS_PARTITION 1
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/*
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* IDE/ATA stuff
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*/
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#undef CONFIG_IDE_RESET /* no reset for ide supported */
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#define CONFIG_SYS_IDE_MAXBUS 1
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#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
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#undef CONFIG_EBIU_AMBCTL1_VAL
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
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#define CONFIG_CF_ATASEL_DIS 0x20311800
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#define CONFIG_CF_ATASEL_ENA 0x20311802
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#if defined(CONFIG_BFIN_TRUE_IDE)
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/*
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* Note that these settings aren't for the most part used in include/ata.h
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* when all of the ATA registers are setup
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*/
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#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
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#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
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#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */
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#elif defined(CONFIG_BFIN_CF_IDE)
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#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
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#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
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#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
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#elif defined(CONFIG_BFIN_HDD_IDE)
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#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
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#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
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#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
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#undef CONFIG_SCLK_DIV
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#define CONFIG_SCLK_DIV 8
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#endif
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#endif
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/*
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* Misc Settings
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*/
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#define CONFIG_MISC_INIT_R
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#define CONFIG_RTC_BFIN
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#define CONFIG_UART_CONSOLE 0
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/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
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/* Define if want to do post memory test */
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#undef CONFIG_POST
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#ifdef CONFIG_POST
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#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
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#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
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#endif
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/* These are for board tests */
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#if 0
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#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_PROMPT \
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"autoboot in %d seconds: press space to stop\n", bootdelay
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#define CONFIG_AUTOBOOT_STOP_STR " "
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#endif
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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#endif
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