upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
210 lines
5.9 KiB
210 lines
5.9 KiB
/*
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* Copyright (C) 2006 Bryan O'Donoghue, CodeHermit
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* bodonoghue@codehermit.ie
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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*/
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#include <commproc.h>
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/* Mode Register */
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#define USMOD_EN 0x01
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#define USMOD_HOST 0x02
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#define USMOD_TEST 0x04
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#define USMOD_SFTE 0x08
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#define USMOD_RESUME 0x40
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#define USMOD_LSS 0x80
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/* Endpoint Registers */
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#define USEP_RHS_NORM 0x00
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#define USEP_RHS_IGNORE 0x01
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#define USEP_RHS_NAK 0x02
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#define USEP_RHS_STALL 0x03
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#define USEP_THS_NORM 0x00
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#define USEP_THS_IGNORE 0x04
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#define USEP_THS_NAK 0x08
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#define USEP_THS_STALL 0x0C
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#define USEP_RTE 0x10
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#define USEP_MF 0x20
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#define USEP_TM_CONTROL 0x00
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#define USEP_TM_INT 0x100
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#define USEP_TM_BULK 0x200
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#define USEP_TM_ISO 0x300
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/* Command Register */
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#define USCOM_EP0 0x00
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#define USCOM_EP1 0x01
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#define USCOM_EP2 0x02
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#define USCOM_EP3 0x03
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#define USCOM_FLUSH 0x40
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#define USCOM_STR 0x80
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/* Event Register */
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#define USB_E_RXB 0x0001
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#define USB_E_TXB 0x0002
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#define USB_E_BSY 0x0004
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#define USB_E_SOF 0x0008
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#define USB_E_TXE1 0x0010
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#define USB_E_TXE2 0x0020
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#define USB_E_TXE3 0x0040
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#define USB_E_TXE4 0x0080
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#define USB_TX_ERRMASK (USB_E_TXE1|USB_E_TXE2|USB_E_TXE3|USB_E_TXE4)
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#define USB_E_IDLE 0x0100
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#define USB_E_RESET 0x0200
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/* Mask Register */
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#define USBS_IDLE 0x01
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/* RX Buffer Descriptor */
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#define RX_BD_OV 0x02
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#define RX_BD_CR 0x04
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#define RX_BD_AB 0x08
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#define RX_BD_NO 0x10
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#define RX_BD_PID_DATA0 0x00
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#define RX_BD_PID_DATA1 0x40
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#define RX_BD_PID_SETUP 0x80
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#define RX_BD_F 0x400
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#define RX_BD_L 0x800
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#define RX_BD_I 0x1000
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#define RX_BD_W 0x2000
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#define RX_BD_E 0x8000
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/* Useful masks */
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#define RX_BD_PID_BITMASK (RX_BD_PID_DATA1 | RX_BD_PID_SETUP)
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#define STALL_BITMASK (USEP_THS_STALL | USEP_RHS_STALL)
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#define NAK_BITMASK (USEP_THS_NAK | USEP_RHS_NAK)
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#define CBD_TX_BITMASK (TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_I | TX_BD_CNF)
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/* TX Buffer Descriptor */
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#define TX_BD_UN 0x02
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#define TX_BD_TO 0x04
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#define TX_BD_NO_PID 0x00
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#define TX_BD_PID_DATA0 0x80
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#define TX_BD_PID_DATA1 0xC0
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#define TX_BD_CNF 0x200
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#define TX_BD_TC 0x400
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#define TX_BD_L 0x800
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#define TX_BD_I 0x1000
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#define TX_BD_W 0x2000
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#define TX_BD_R 0x8000
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/* Implementation specific defines */
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#define EP_MIN_PACKET_SIZE 0x08
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#define MAX_ENDPOINTS 0x04
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#define FIFO_SIZE 0x10
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#define EP_MAX_PKT FIFO_SIZE
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#define TX_RING_SIZE 0x04
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#define RX_RING_SIZE 0x06
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#define USB_MAX_PKT 0x40
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#define TOGGLE_TX_PID(x) x= ((~x)&0x40)|0x80
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#define TOGGLE_RX_PID(x) x^= 0x40
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#define EP_ATTACHED 0x01 /* Endpoint has a urb attached or not */
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#define EP_SEND_ZLP 0x02 /* Send ZLP y/n ? */
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#define PROFF_USB 0x00000000
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#define CPM_USB_BASE 0x00000A00
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/* UDC device defines */
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#define EP0_MAX_PACKET_SIZE EP_MAX_PKT
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#define UDC_OUT_ENDPOINT 0x02
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#define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE
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#define UDC_IN_ENDPOINT 0x03
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#define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE
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#define UDC_INT_ENDPOINT 0x01
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#define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE
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#define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE
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struct mpc8xx_ep {
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struct urb * urb;
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unsigned char pid;
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unsigned char sc;
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volatile cbd_t * prx;
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};
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typedef struct mpc8xx_usb{
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char usmod; /* Mode Register */
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char usaddr; /* Slave Address Register */
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char uscom; /* Command Register */
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char res1; /* Reserved */
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ushort usep[4];
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ulong res2; /* Reserved */
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ushort usber; /* Event Register */
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ushort res3; /* Reserved */
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ushort usbmr; /* Mask Register */
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char res4; /* Reserved */
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char usbs; /* Status Register */
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char res5[8]; /* Reserved */
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}usb_t;
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typedef struct mpc8xx_parameter_ram{
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ushort ep0ptr; /* Endpoint Pointer Register 0 */
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ushort ep1ptr; /* Endpoint Pointer Register 1 */
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ushort ep2ptr; /* Endpoint Pointer Register 2 */
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ushort ep3ptr; /* Endpoint Pointer Register 3 */
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uint rstate; /* Receive state */
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uint rptr; /* Receive internal data pointer */
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ushort frame_n; /* Frame number */
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ushort rbcnt; /* Receive byte count */
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uint rtemp; /* Receive temp cp use only */
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uint rxusb; /* Rx Data Temp */
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ushort rxuptr; /* Rx microcode return address temp */
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}usb_pram_t;
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typedef struct endpoint_parameter_block_pointer{
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ushort rbase; /* RxBD base address */
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ushort tbase; /* TxBD base address */
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char rfcr; /* Rx Function code */
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char tfcr; /* Tx Function code */
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ushort mrblr; /* Maximum Receive Buffer Length */
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ushort rbptr; /* RxBD pointer Next Buffer Descriptor */
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ushort tbptr; /* TxBD pointer Next Buffer Descriptor */
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ulong tstate; /* Transmit internal state */
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ulong tptr; /* Transmit internal data pointer */
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ushort tcrc; /* Transmit temp CRC */
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ushort tbcnt; /* Transmit internal bye count */
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ulong ttemp; /* Tx temp */
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ushort txuptr; /* Tx microcode return address */
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ushort res1; /* Reserved */
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}usb_epb_t;
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typedef enum mpc8xx_udc_state{
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STATE_NOT_READY,
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STATE_ERROR,
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STATE_READY,
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}mpc8xx_udc_state_t;
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/* Declarations */
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int udc_init(void);
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void udc_irq(void);
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int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
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void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
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struct usb_endpoint_instance *endpoint);
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void udc_connect(void);
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void udc_disconnect(void);
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void udc_enable(struct usb_device_instance *device);
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void udc_disable(void);
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void udc_startup_events(struct usb_device_instance *device);
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/* Flow control */
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void udc_set_nak(int epid);
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void udc_unset_nak (int epid);
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