upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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362 lines
12 KiB
362 lines
12 KiB
/*
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* (C) Copyright 2002,2003 Motorola,Inc.
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* Modified by Lunsheng Wang, lunsheng@sohu.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* mpc8540eval board configuration file */
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/* please refer to doc/README.mpc85xxads for more info */
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/* make sure you change the MAC address and other network params first,
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* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
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#define CONFIG_MPC8540 1 /* MPC8540 specific */
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#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */
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#undef CONFIG_PCI /* pci ethernet support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#undef CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_DDR_DLL /* possible DLL fix needed */
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/* Using Localbus SDRAM to emulate flash before we can program the flash,
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* normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
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* Not availabe for EVAL board
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*/
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#undef CONFIG_RAM_AS_FLASH
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/* sysclk for MPC8540EVAL */
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#if defined(CONFIG_SYSCLK_66M)
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/*
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* the oscillator on board is 66Mhz
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* can also get 66M clock from external PCI
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*/
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#define CONFIG_SYS_CLK_FREQ 66000000
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#else
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#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
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#endif
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/* below can be toggled for performance analysis. otherwise use default */
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#undef CONFIG_BTB /* toggle branch predition */
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#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
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#undef CFG_DRAM_TEST /* memory test, takes time */
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#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00400000
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#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
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#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
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#endif
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
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#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
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#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
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#define CFG_SDRAM_SIZE 256 /* DDR is now 256MB */
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#if defined(CONFIG_RAM_AS_FLASH)
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#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
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#else
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#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
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#endif
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#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */
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#if defined(CONFIG_RAM_AS_FLASH)
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#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
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#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
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#else /* Boot from real Flash */
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#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
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#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */
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#endif
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#define CFG_OR0_PRELIM 0xff806f67 /* 8MB Flash */
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
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#define CFG_FLASH_CFI 1
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT
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#else
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#undef CFG_RAMBOOT
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#endif
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
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/* Here some DDR setting should be added */
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#undef CONFIG_CLOCKS_IN_MHZ
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/* local bus definitions */
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#define CFG_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
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#define CFG_OR2_PRELIM 0xfc006901
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#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/
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#define CFG_LBC_LBCR 0x00000000
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#define CFG_LBC_LSRT 0x20000000
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#define CFG_LBC_MRTPR 0x20000000
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#define CFG_LBC_LSDMR_1 0x2861b723
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#define CFG_LBC_LSDMR_2 0x0861b723
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#define CFG_LBC_LSDMR_3 0x0861b723
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#define CFG_LBC_LSDMR_4 0x1861b723
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#define CFG_LBC_LSDMR_5 0x4061b723
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#if defined(CONFIG_RAM_AS_FLASH)
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#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
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#else
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#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
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#endif
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#define CFG_OR4_PRELIM 0xffffe1f1
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#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
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#define CONFIG_L1_INIT_RAM
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#define CFG_INIT_RAM_LOCK 1
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#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
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#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
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/* Use the HUSH parser */
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#define CFG_HUSH_PARSER
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/*
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* I2C
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*/
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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/* General PCI */
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#define CFG_PCI_MEM_BASE 0x80000000
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#define CFG_PCI_MEM_PHYS 0x80000000
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#define CFG_PCI_MEM_SIZE 0x20000000
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#define CFG_PCI_IO_BASE 0xe2000000
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#if defined(CONFIG_PCI)
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#define CONFIG_NET_MULTI
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#undef CONFIG_EEPRO100
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#define CONFIG_TULIP
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#if !defined(CONFIG_PCI_PNP)
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#define PCI_ENET0_IOADDR 0xe0000000
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#define PCI_ENET0_MEMADDR 0xe0000000
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#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
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#endif
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0008
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#elif defined(CONFIG_TSEC_ENET)
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#define CONFIG_NET_MULTI 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_MPC85XX_FEC 1
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#define CONFIG_MPC85XX_FEC_NAME "FEC"
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#define TSEC1_PHY_ADDR 7
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#define TSEC2_PHY_ADDR 4
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#define FEC_PHY_ADDR 2
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define FEC_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define FEC_FLAGS 0
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/* Options are: TSEC[0-1], FEC */
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#define CONFIG_ETHPRIME "TSEC0"
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#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
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#define INTEL_LXT971_PHY 1
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#endif
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#undef DEBUG
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/* Environment */
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#ifndef CFG_RAMBOOT
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#if defined(CONFIG_RAM_AS_FLASH)
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#define CFG_ENV_IS_NOWHERE
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
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#define CFG_ENV_SIZE 0x2000
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#else
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
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#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
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#endif
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#define CFG_ENV_SIZE 0x2000
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#else
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/* #define CFG_NO_FLASH 1 */ /* Flash is not usable now */
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#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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#define CFG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
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#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
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#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
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#undef CONFIG_CMD_ENV
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#undef CONFIG_CMD_LOADS
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_LOAD_ADDR 0x2000000 /* default load address */
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#define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/* Cache Configuration */
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#define CFG_DCACHE_SIZE 32768
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#define CFG_CACHELINE_SIZE 32
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*****************************/
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/* Environment Configuration */
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/*****************************/
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/* The mac addresses for all ethernet interface */
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/* NOTE: change below for your network setting!!! */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_ETHADDR 00:01:af:07:9b:8a
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#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
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#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
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#endif
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#define CONFIG_ROOTPATH /nfsroot
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#define CONFIG_BOOTFILE your.uImage
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#define CONFIG_SERVERIP 192.168.101.1
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#define CONFIG_IPADDR 192.168.101.11
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#define CONFIG_GATEWAYIP 192.168.101.0
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
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#define CONFIG_HOSTNAME MPC8540EVAL
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#endif /* __CONFIG_H */
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