upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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288 lines
8.6 KiB
288 lines
8.6 KiB
/*
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* Copyright (C) 2004 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* U-Boot configuration for Embedded Planet EP8248 boards.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MPC8248
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#define CPU_ID_STR "MPC8248"
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#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
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#undef DEBUG
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
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#define CONFIG_ENV_OVERWRITE
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/*
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* Select serial console configuration
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*
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* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*/
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#define CONFIG_CONS_ON_SMC /* Console is on SMC */
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#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
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#undef CONFIG_CONS_NONE /* It's not on external UART */
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#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
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#define CFG_BCSR 0xFA000000
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/*
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* Select ethernet configuration
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*
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* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
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* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
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* SCC, 1-3 for FCC)
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*
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* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
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* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
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* must be unset.
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*/
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#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
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#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
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#undef CONFIG_ETHER_NONE /* No external Ethernet */
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#ifdef CONFIG_ETHER_ON_FCC
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#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
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#if (CONFIG_ETHER_INDEX == 1)
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/* - Rx clock is CLK10
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* - Tx clock is CLK11
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* - BDs/buffers on 60x bus
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* - Full duplex
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*/
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#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
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#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
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#define CFG_CPMFCR_RAMTYPE 0
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#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#elif (CONFIG_ETHER_INDEX == 2)
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/* - Rx clock is CLK13
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* - Tx clock is CLK14
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* - BDs/buffers on 60x bus
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* - Full duplex
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*/
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#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
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#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
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#define CFG_CPMFCR_RAMTYPE 0
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#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#endif /* CONFIG_ETHER_INDEX */
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
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/*
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* GPIO pins used for bit-banged MII communications
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*/
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#define MDIO_PORT 0 /* Not used - implemented in BCSR */
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#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
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#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04)
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#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1)
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#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
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else *(vu_char *)(CFG_BCSR + 8) &= 0xFE
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#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
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else *(vu_char *)(CFG_BCSR + 8) &= 0xFD
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#define MIIDELAY udelay(1)
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#endif /* CONFIG_ETHER_ON_FCC */
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#ifndef CONFIG_8260_CLKIN
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#define CONFIG_8260_CLKIN 66000000 /* in Hz */
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#endif
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#define CONFIG_BAUDRATE 38400
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
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#if defined(CONFIG_CMD_KGDB)
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#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
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#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
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#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
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#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
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#endif
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#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
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#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CFG_FLASH_BASE 0xFF800000
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#define CFG_FLASH_CFI
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
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#define CFG_DIRECT_FLASH_TFTP
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#if defined(CONFIG_CMD_JFFS2)
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#define CFG_JFFS2_FIRST_BANK 0
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#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
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#define CFG_JFFS2_FIRST_SECTOR 0
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#define CFG_JFFS2_LAST_SECTOR 62
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#define CFG_JFFS2_SORT_FRAGMENTS
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#define CFG_JFFS_CUSTOM_PART
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#endif
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#if defined(CONFIG_CMD_I2C)
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#define CONFIG_HARD_I2C 1 /* To enable I2C support */
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#define CFG_I2C_SPEED 100000 /* I2C speed */
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#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
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#endif
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT
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#endif
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
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#define CFG_ENV_IS_IN_FLASH
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x20000
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#endif /* CFG_ENV_IS_IN_FLASH */
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#define CFG_DEFAULT_IMMR 0x00010000
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#define CFG_IMMR 0xF0000000
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/* Hard reset configuration word */
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#define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
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/* No slaves */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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#define CFG_HRCW_SLAVE3 0
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#define CFG_HRCW_SLAVE4 0
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#define CFG_HRCW_SLAVE5 0
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#define CFG_HRCW_SLAVE6 0
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#define CFG_HRCW_SLAVE7 0
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#define CFG_HID0_INIT 0
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#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
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#define CFG_HID2 0
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#define CFG_SIUMCR 0x01240200
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#define CFG_SYPCR 0xFFFF0683
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#define CFG_BCR 0x00000000
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#define CFG_SCCR SCCR_DFBRG01
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#define CFG_RMR RMR_CSRE
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#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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#define CFG_RCCR 0
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#define CFG_MPTPR 0x1300
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#define CFG_PSDMR 0x82672522
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#define CFG_PSRT 0x4B
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00001841)
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#define CFG_SDRAM_OR 0xFF0030C0
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801)
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#define CFG_OR0_PRELIM 0xFF8008C2
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#define CFG_BR2_PRELIM (CFG_BCSR | 0x00000801)
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#define CFG_OR2_PRELIM 0xFFF00864
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#define CFG_RESET_ADDRESS 0xC0000000
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#endif /* __CONFIG_H */
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