upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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264 lines
14 KiB
264 lines
14 KiB
/*
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*
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* BRIEF MODULE DESCRIPTION
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* OMAP730 hardware map
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*
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* Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
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* Author: MPC-Data Limited
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* Dave Peverley
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __INCLUDED_OMAP730_H
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#define __INCLUDED_OMAP730_H
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#include <asm/arch/sizes.h>
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/***************************************************************************
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* OMAP730 Configuration Registers
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**************************************************************************/
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#define PERSEUS2_MPU_DEV_ID ((unsigned int)(0xFFFE1000))
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#define PERSEUS2_GSM_DEV_ID0 ((unsigned int)(0xFFFE1000))
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#define PERSEUS2_GDM_DEV_ID1 ((unsigned int)(0xFFFE1002))
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#define DSP_CONF ((unsigned int)(0xFFFE1004))
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#define PERSEUS2_MPU_DIE_ID0 ((unsigned int)(0xFFFE1008))
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#define GSM_ASIC_CONF ((unsigned int)(0xFFFE1008))
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#define PERSEUS2_MPU_DIE_ID1 ((unsigned int)(0xFFFE100C))
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#define PERSEUS2_MODE1 ((unsigned int)(0xFFFE1010))
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#define PERSEUS2_GSM_DIE_ID0 ((unsigned int)(0xFFFE1010))
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#define PERSEUS2_GSM_DIE_ID1 ((unsigned int)(0xFFFE1012))
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#define PERSEUS2_MODE2 ((unsigned int)(0xFFFE1014))
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#define PERSEUS2_GSM_DIE_ID2 ((unsigned int)(0xFFFE1014))
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#define PERSEUS2_GSM_DIE_ID3 ((unsigned int)(0xFFFE1016))
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#define PERSEUS2_ANALOG_CELLS_CONF ((unsigned int)(0xFFFE1018))
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#define SPECCTL ((unsigned int)(0xFFFE101C))
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#define SPARE1 ((unsigned int)(0xFFFE1020))
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#define SPARE2 ((unsigned int)(0xFFFE1024))
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#define GSM_PBG_IRQ ((unsigned int)(0xFFFE1028))
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#define DMA_REQ_CONF ((unsigned int)(0xFFFE1030))
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#define PE_CONF_NO_DUAL ((unsigned int)(0xFFFE1060))
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#define PERSEUS2_IO_CONF0 ((unsigned int)(0xFFFE1070))
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#define PERSEUS2_IO_CONF1 ((unsigned int)(0xFFFE1074))
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#define PERSEUS2_IO_CONF2 ((unsigned int)(0xFFFE1078))
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#define PERSEUS2_IO_CONF3 ((unsigned int)(0xFFFE107C))
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#define PERSEUS2_IO_CONF4 ((unsigned int)(0xFFFE1080))
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#define PERSEUS2_IO_CONF5 ((unsigned int)(0xFFFE1084))
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#define PERSEUS2_IO_CONF6 ((unsigned int)(0xFFFE1088))
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#define PERSEUS2_IO_CONF7 ((unsigned int)(0xFFFE108C))
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#define PERSEUS2_IO_CONF8 ((unsigned int)(0xFFFE1090))
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#define PERSEUS2_IO_CONF9 ((unsigned int)(0xFFFE1094))
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#define PERSEUS2_IO_CONF10 ((unsigned int)(0xFFFE1098))
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#define PERSEUS2_IO_CONF11 ((unsigned int)(0xFFFE109C))
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#define PERSEUS2_IO_CONF12 ((unsigned int)(0xFFFE10A0))
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#define PERSEUS2_IO_CONF13 ((unsigned int)(0xFFFE10A4))
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#define PERSEUS_PCC_CONF_REG ((unsigned int)(0xFFFE10B4))
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#define BIST_STATUS_INTERNAL ((unsigned int)(0xFFFE10B8))
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#define BIST_CONTROL ((unsigned int)(0xFFFE10C0))
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#define BOOT_ROM_REG ((unsigned int)(0xFFFE10C4))
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#define PRODUCTION_ID_REG ((unsigned int)(0xFFFE10C8))
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#define BIST_SECROM_SIGNATURE1_INTERNAL ((unsigned int)(0xFFFE10D0))
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#define BIST_SECROM_SIGNATURE2_INTERNAL ((unsigned int)(0xFFFE10D4))
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#define BIST_CONTROL_2 ((unsigned int)(0xFFFE10D8))
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#define DEBUG1 ((unsigned int)(0xFFFE10E0))
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#define DEBUG2 ((unsigned int)(0xFFFE10E4))
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#define DEBUG_DMA_IRQ ((unsigned int)(0xFFFE10E8))
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/***************************************************************************
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* OMAP730 EMIFS Registers (TRM 2.5.7)
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**************************************************************************/
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#define TCMIF_BASE 0xFFFECC00
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#define EMIFS_LRUREG (TCMIF_BASE + 0x04)
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#define EMIFS_CONFIG (TCMIF_BASE + 0x0C)
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#define FLASH_CFG_0 (TCMIF_BASE + 0x10)
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#define FLASH_CFG_1 (TCMIF_BASE + 0x14)
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#define FLASH_CFG_2 (TCMIF_BASE + 0x18)
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#define FLASH_CFG_3 (TCMIF_BASE + 0x1C)
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#define FL_CFG_DYN_WAIT (TCMIF_BASE + 0x40)
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#define EMIFS_TIMEOUT1_REG (TCMIF_BASE + 0x28)
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#define EMIFS_TIMEOUT2_REG (TCMIF_BASE + 0x2C)
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#define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30)
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#define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44)
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#define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48)
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#define EMIFS_ABORT_TOUT (TCMIF_BASE + 0x4C)
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#define FLASH_ACFG_0_1 (TCMIF_BASE + 0x50)
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#define FLASH_ACFG_1_1 (TCMIF_BASE + 0x54)
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#define FLASH_ACFG_2_1 (TCMIF_BASE + 0x58)
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#define FLASH_ACFG_3_1 (TCMIF_BASE + 0x5C)
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/***************************************************************************
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* OMAP730 Interrupt handlers
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**************************************************************************/
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#define OMAP_IH1_BASE 0xFFFECB00 /* MPU Level 1 IRQ handler */
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#define OMAP_IH2_BASE 0xfffe0000
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/***************************************************************************
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* OMAP730 Timers
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*
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* There are three general purpose OS timers in the 730 that can be
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* configured in autoreload or one-shot modes.
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**************************************************************************/
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#define OMAP730_32kHz_TIMER_BASE 0xFFFB9000
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/* 32k Timer Registers */
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#define TIMER32k_CR 0x08
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#define TIMER32k_TVR 0x00
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#define TIMER32k_TCR 0x04
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/* 32k Timer Control Register definition */
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#define TIMER32k_TSS (1<<0)
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#define TIMER32k_TRB (1<<1)
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#define TIMER32k_INT (1<<2)
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#define TIMER32k_ARL (1<<3)
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/* MPU Timer base addresses */
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#define OMAP730_MPUTIMER_BASE 0xfffec500
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#define OMAP730_MPUTIMER_OFF 0x00000100
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#define OMAP730_TIMER1_BASE 0xFFFEC500
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#define OMAP730_TIMER2_BASE 0xFFFEC600
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#define OMAP730_TIMER3_BASE 0xFFFEC700
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/* MPU Timer Register offsets */
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#define CNTL_TIMER 0x00 /* MPU_CNTL_TIMER */
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#define LOAD_TIM 0x04 /* MPU_LOAD_TIMER */
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#define READ_TIM 0x08 /* MPU_READ_TIMER */
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/* MPU_CNTL_TIMER register bits */
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#define MPUTIM_FREE (1<<6)
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#define MPUTIM_CLOCK_ENABLE (1<<5)
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#define MPUTIM_PTV_MASK (0x7<<PTV_BIT)
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#define MPUTIM_PTV_BIT 2
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#define MPUTIM_AR (1<<1)
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#define MPUTIM_ST (1<<0)
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/***************************************************************************
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* OMAP730 GPIO
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*
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* The GPIO control is split over 6 register bases in the OMAP730 to allow
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* access to all the (6 x 32) GPIO pins!
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**************************************************************************/
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#define OMAP730_GPIO_BASE_1 0xFFFBC000
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#define OMAP730_GPIO_BASE_2 0xFFFBC800
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#define OMAP730_GPIO_BASE_3 0xFFFBD000
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#define OMAP730_GPIO_BASE_4 0xFFFBD800
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#define OMAP730_GPIO_BASE_5 0xFFFBE000
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#define OMAP730_GPIO_BASE_6 0xFFFBE800
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#define GPIO_DATA_INPUT 0x00
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#define GPIO_DATA_OUTPUT 0x04
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#define GPIO_DIRECTION_CONTROL 0x08
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#define GPIO_INTERRUPT_CONTROL 0x0C
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#define GPIO_INTERRUPT_MASK 0x10
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#define GPIO_INTERRUPT_STATUS 0x14
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#define GPIO_DATA_INPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
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#define GPIO_DATA_OUTPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
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#define GPIO_DIRECTION_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
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#define GPIO_INTERRUPT_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
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#define GPIO_INTERRUPT_MASK_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
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#define GPIO_INTERRUPT_STATUS_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
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#define GPIO_DATA_INPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
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#define GPIO_DATA_OUTPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
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#define GPIO_DIRECTION_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
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#define GPIO_INTERRUPT_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
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#define GPIO_INTERRUPT_MASK_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
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#define GPIO_INTERRUPT_STATUS_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
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#define GPIO_DATA_INPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
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#define GPIO_DATA_OUTPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
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#define GPIO_DIRECTION_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
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#define GPIO_INTERRUPT_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
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#define GPIO_INTERRUPT_MASK_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
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#define GPIO_INTERRUPT_STATUS_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
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#define GPIO_DATA_INPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
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#define GPIO_DATA_OUTPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
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#define GPIO_DIRECTION_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
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#define GPIO_INTERRUPT_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
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#define GPIO_INTERRUPT_MASK_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
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#define GPIO_INTERRUPT_STATUS_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
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#define GPIO_DATA_INPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
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#define GPIO_DATA_OUTPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
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#define GPIO_DIRECTION_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
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#define GPIO_INTERRUPT_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
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#define GPIO_INTERRUPT_MASK_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
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#define GPIO_INTERRUPT_STATUS_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
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#define GPIO_DATA_INPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
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#define GPIO_DATA_OUTPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
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#define GPIO_DIRECTION_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
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#define GPIO_INTERRUPT_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
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#define GPIO_INTERRUPT_MASK_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
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#define GPIO_INTERRUPT_STATUS_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
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/***************************************************************************
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* OMAP730 Watchdog timers
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**************************************************************************/
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#define WDTIM_BASE 0xFFFEC800
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#define WDTIM_CONTROL (WDTIM_BASE + 0x00) /* MPU_CNTL_TIMER */
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#define WDTIM_LOAD (WDTIM_BASE + 0x04) /* MPU_LOAD_TIMER */
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#define WDTIM_READ (WDTIM_BASE + 0x04) /* MPU_READ_TIMER */
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#define WDTIM_MODE (WDTIM_BASE + 0x08) /* MPU_TIMER_MODE */
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/***************************************************************************
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* OMAP730 Interrupt Registers
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**************************************************************************/
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/* Interrupt Register offsets */
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#define IRQ_ITR 0x00
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#define IRQ_MIR 0x04
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#define IRQ_SIR_IRQ 0x10
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#define IRQ_SIR_FIQ 0x14
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#define IRQ_CONTROL_REG 0x18
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#define IRQ_ILR0 0x1C /* ILRx == ILR0 + (0x4 * x) */
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#define IRQ_SIR 0x9C /* a.k.a.IRQ_ISR */
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#define IRQ_GMIR 0xA0
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#define REG_IHL1_MIR (OMAP_IH1_BASE + IRQ_MIR)
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#define REG_IHL2_MIR (OMAP_IH2_BASE + IRQ_MIR)
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/***************************************************************************
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* OMAP730 Intersystem Communication Register (TRM 4.5)
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**************************************************************************/
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#define ICR_BASE 0xFFFBB800
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#define M_ICR (ICR_BASE + 0x00)
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#define G_ICR (ICR_BASE + 0x02)
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#define M_CTL (ICR_BASE + 0x04)
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#define G_CTL (ICR_BASE + 0x06)
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#define PM_BA (ICR_BASE + 0x0A)
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#define DM_BA (ICR_BASE + 0x0C)
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#define RM_BA (ICR_BASE + 0x0E)
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#define SSPI_TAS (ICR_BASE + 0x12)
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#endif /* ! __INCLUDED_OMAP730_H */
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