upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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244 lines
7.5 KiB
244 lines
7.5 KiB
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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* Gary Jennejohn <gj@denx.de>
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* David Mueller <d.mueller@elsoft.ch>
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*
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* Modified for the friendly-arm SBC-2410X by
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* (C) Copyright 2005
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* JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
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*
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* Configuation settings for the friendly-arm SBC-2410X board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* If we are developing, we might want to start armboot from ram
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* so we MUST NOT initialize critical regs like mem-timing ...
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*/
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#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
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#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
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#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
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/* input clock of PLL */
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#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
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#define USE_920T_MMU 1
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
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#define CS8900_BASE 0x19000300
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#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
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/*
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* select serial console configuration
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*/
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#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */
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/************************************************************
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* RTC
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************************************************************/
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#define CONFIG_RTC_S3C24X0 1
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
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#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.0.69
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#define CONFIG_SERVERIP 192.168.0.1
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/*#define CONFIG_BOOTFILE "elinos-lart" */
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#define CONFIG_BOOTCOMMAND "dhcp; bootm"
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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/* what's this ? it's not used anywhere */
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#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
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#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR 0x33000000 /* default load address */
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/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
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/* it to wrap 100 times (total 1562500) to get 1 sec. */
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#define CFG_HZ 1562500
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define CFG_FLASH_BASE PHYS_FLASH_1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */
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#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#ifdef CONFIG_AMD_LV800
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#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
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#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
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#endif
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#ifdef CONFIG_AMD_LV400
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#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
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#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
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#endif
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
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/*-----------------------------------------------------------------------
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* NAND flash settings
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*/
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#if defined(CONFIG_CMD_NAND)
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define NAND_WAIT_READY(nand) NF_WaitRB()
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#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
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#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
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#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
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#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
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#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
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#define WRITE_NAND(d, adr) NF_Write(d)
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#define READ_NAND(adr) NF_Read()
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/* the following functions are NOP's because S3C24X0 handles this in hardware */
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#define NAND_CTL_CLRALE(nandptr)
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#define NAND_CTL_SETALE(nandptr)
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#define NAND_CTL_CLRCLE(nandptr)
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#define NAND_CTL_SETCLE(nandptr)
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/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
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#endif /* CONFIG_CMD_NAND */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_CMDLINE_TAG
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CONFIG_CMDLINE_EDITING
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#ifdef CONFIG_CMDLINE_EDITING
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#undef CONFIG_AUTO_COMPLETE
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#else
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#define CONFIG_AUTO_COMPLETE
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#endif
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#endif /* __CONFIG_H */
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