upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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94 lines
1.7 KiB
94 lines
1.7 KiB
/*
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* (C) Copyright 2009
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* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#define TWS_IMPLEMENTATION
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#include <common.h>
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/*=====================================================================*/
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/* Public Functions */
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/*=====================================================================*/
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/*-----------------------------------------------------------------------
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* Read bits
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*/
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int tws_read(uchar *buffer, int len)
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{
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int rem = len;
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uchar accu, shift;
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debug("tws_read: buffer %p len %d\n", buffer, len);
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/* Configure the data pin for input */
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tws_data_config_output(0);
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/* Disable WR, i.e. setup a read */
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tws_wr(0);
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udelay(1);
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/* Rise CE */
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tws_ce(1);
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udelay(1);
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for (; rem > 0; ) {
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for (shift = 0, accu = 0;
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(rem > 0) && (shift < 8);
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rem--, shift++) {
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tws_clk(1);
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udelay(10);
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accu |= (tws_data_read() << shift); /* LSB first */
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tws_clk(0);
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udelay(10);
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}
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*buffer++ = accu;
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}
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/* Lower CE */
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tws_ce(0);
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return len - rem;
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}
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/*-----------------------------------------------------------------------
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* Write bits
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*/
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int tws_write(uchar *buffer, int len)
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{
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int rem = len;
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uchar accu, shift;
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debug("tws_write: buffer %p len %d\n", buffer, len);
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/* Configure the data pin for output */
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tws_data_config_output(1);
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/* Enable WR, i.e. setup a write */
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tws_wr(1);
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udelay(1);
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/* Rise CE */
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tws_ce(1);
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udelay(1);
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for (; rem > 0; ) {
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for (shift = 0, accu = *buffer++;
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(rem > 0) && (shift < 8);
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rem--, shift++) {
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tws_data(accu & 0x01); /* LSB first */
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tws_clk(1);
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udelay(10);
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tws_clk(0);
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udelay(10);
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accu >>= 1;
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}
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}
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/* Lower CE */
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tws_ce(0);
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return len - rem;
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}
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