upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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640 lines
14 KiB
640 lines
14 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <commproc.h>
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#include <command.h>
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#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
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#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
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#define SMC_INDEX 0
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#undef SCC_INDEX
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#define PROFF_SMC PROFF_SMC1
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#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
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#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
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#define SMC_INDEX 1
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#undef SCC_INDEX
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#define PROFF_SMC PROFF_SMC2
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#define CPM_CR_CH_SMC CPM_CR_CH_SMC2
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#elif defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
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#undef SMC_INDEX
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#define SCC_INDEX 0
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#define PROFF_SCC PROFF_SCC1
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#define CPM_CR_CH_SCC CPM_CR_CH_SCC1
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#elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
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#undef SMC_INDEX
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#define SCC_INDEX 1
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#define PROFF_SCC PROFF_SCC2
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#define CPM_CR_CH_SCC CPM_CR_CH_SCC2
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#elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
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#undef SMC_INDEX
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#define SCC_INDEX 2
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#define PROFF_SCC PROFF_SCC3
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#define CPM_CR_CH_SCC CPM_CR_CH_SCC3
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#elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
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#undef SMC_INDEX
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#define SCC_INDEX 3
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#define PROFF_SCC PROFF_SCC4
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#define CPM_CR_CH_SCC CPM_CR_CH_SCC4
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#else /* CONFIG_8xx_CONS_? */
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#error "console not correctly defined"
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#endif
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#if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
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/*
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* Minimal serial functions needed to use one of the SMC ports
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* as serial console interface.
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*/
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int serial_init (void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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volatile smc_t *sp;
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volatile smc_uart_t *up;
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volatile cbd_t *tbdf, *rbdf;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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#if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
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volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
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#endif
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uint dpaddr;
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/* initialize pointers to SMC */
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sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
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up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
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/* Disable transmitter/receiver.
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*/
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sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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/* Enable SDMA.
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*/
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im->im_siu_conf.sc_sdcr = 1;
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/* clear error conditions */
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#ifdef CFG_SDSR
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im->im_sdma.sdma_sdsr = CFG_SDSR;
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#else
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im->im_sdma.sdma_sdsr = 0x83;
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#endif
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/* clear SDMA interrupt mask */
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#ifdef CFG_SDMR
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im->im_sdma.sdma_sdmr = CFG_SDMR;
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#else
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im->im_sdma.sdma_sdmr = 0x00;
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#endif
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#if defined(CONFIG_8xx_CONS_SMC1)
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/* Use Port B for SMC1 instead of other functions.
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*/
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cp->cp_pbpar |= 0x000000c0;
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cp->cp_pbdir &= ~0x000000c0;
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cp->cp_pbodr &= ~0x000000c0;
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#else /* CONFIG_8xx_CONS_SMC2 */
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# if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
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/* Use Port A for SMC2 instead of other functions.
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*/
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ip->iop_papar |= 0x00c0;
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ip->iop_padir &= ~0x00c0;
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ip->iop_paodr &= ~0x00c0;
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# else /* must be a 860 then */
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/* Use Port B for SMC2 instead of other functions.
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*/
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cp->cp_pbpar |= 0x00000c00;
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cp->cp_pbdir &= ~0x00000c00;
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cp->cp_pbodr &= ~0x00000c00;
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# endif
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#endif
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#if defined(CONFIG_FADS)
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/* Enable RS232 */
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#if defined(CONFIG_8xx_CONS_SMC1)
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*((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
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#else
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*((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
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#endif
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#endif /* CONFIG_FADS */
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#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
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/* Enable Monitor Port Transceiver */
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*((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
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#endif /* CONFIG_RPXLITE */
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/* Set the physical address of the host memory buffers in
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* the buffer descriptors.
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*/
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#ifdef CFG_ALLOC_DPRAM
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dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
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#else
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dpaddr = CPM_SERIAL_BASE ;
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#endif
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/* Allocate space for two buffer descriptors in the DP ram.
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* For now, this address seems OK, but it may have to
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* change with newer versions of the firmware.
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* damm: allocating space after the two buffers for rx/tx data
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*/
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rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
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rbdf->cbd_bufaddr = (uint) (rbdf+2);
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rbdf->cbd_sc = 0;
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tbdf = rbdf + 1;
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tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
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tbdf->cbd_sc = 0;
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/* Set up the uart parameters in the parameter ram.
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*/
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up->smc_rbase = dpaddr;
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up->smc_tbase = dpaddr+sizeof(cbd_t);
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up->smc_rfcr = SMC_EB;
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up->smc_tfcr = SMC_EB;
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#if defined(CONFIG_MBX)
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board_serial_init();
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#endif /* CONFIG_MBX */
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/* Set UART mode, 8 bit, no parity, one stop.
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* Enable receive and transmit.
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*/
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sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
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/* Mask all interrupts and remove anything pending.
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*/
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sp->smc_smcm = 0;
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sp->smc_smce = 0xff;
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/* Set up the baud rate generator.
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*/
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serial_setbrg ();
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/* Make the first buffer the only buffer.
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*/
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tbdf->cbd_sc |= BD_SC_WRAP;
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rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
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/* Single character receive.
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*/
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up->smc_mrblr = 1;
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up->smc_maxidl = 0;
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/* Initialize Tx/Rx parameters.
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*/
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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/* Enable transmitter/receiver.
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*/
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sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
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return (0);
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}
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void
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serial_setbrg (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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/* Set up the baud rate generator.
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* See 8xx_io/commproc.c for details.
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*
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* Wire BRG1 to SMCx
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*/
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cp->cp_simode = 0x00000000;
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cp->cp_brgc1 =
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(((gd->cpu_clk / 16 / gd->baudrate)-1) << 1) | CPM_BRG_EN;
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}
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void
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serial_putc(const char c)
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{
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volatile cbd_t *tbdf;
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volatile char *buf;
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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volatile cpm8xx_t *cpmp = &(im->im_cpm);
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if (c == '\n')
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serial_putc ('\r');
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up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
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tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
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/* Wait for last character to go.
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*/
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buf = (char *)tbdf->cbd_bufaddr;
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#if 0
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__asm__("eieio");
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while (tbdf->cbd_sc & BD_SC_READY)
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__asm__("eieio");
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#endif
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*buf = c;
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tbdf->cbd_datlen = 1;
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tbdf->cbd_sc |= BD_SC_READY;
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__asm__("eieio");
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#if 1
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while (tbdf->cbd_sc & BD_SC_READY)
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__asm__("eieio");
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#endif
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}
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int
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serial_getc(void)
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{
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volatile cbd_t *rbdf;
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volatile unsigned char *buf;
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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volatile cpm8xx_t *cpmp = &(im->im_cpm);
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unsigned char c;
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up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
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rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
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/* Wait for character to show up.
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*/
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buf = (unsigned char *)rbdf->cbd_bufaddr;
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while (rbdf->cbd_sc & BD_SC_EMPTY)
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;
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c = *buf;
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rbdf->cbd_sc |= BD_SC_EMPTY;
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return(c);
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}
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int
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serial_tstc()
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{
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volatile cbd_t *rbdf;
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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volatile cpm8xx_t *cpmp = &(im->im_cpm);
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up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
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rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
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return(!(rbdf->cbd_sc & BD_SC_EMPTY));
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}
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#else /* ! CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
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int serial_init (void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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volatile scc_t *sp;
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volatile scc_uart_t *up;
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volatile cbd_t *tbdf, *rbdf;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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uint dpaddr;
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#if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
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volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
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#endif
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/* initialize pointers to SCC */
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sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
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up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
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#if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
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{ /* Disable Ethernet, enable Serial */
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uchar c;
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c = pic_read (0x61);
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c &= ~0x40; /* enable COM3 */
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c |= 0x80; /* disable Ethernet */
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pic_write (0x61, c);
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/* enable RTS2 */
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cp->cp_pbpar |= 0x2000;
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cp->cp_pbdat |= 0x2000;
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cp->cp_pbdir |= 0x2000;
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}
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#endif /* CONFIG_LWMON */
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/* Disable transmitter/receiver.
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*/
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sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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#if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
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/*
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* The MPC850 has SCC3 on Port B
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*/
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cp->cp_pbpar |= 0x06;
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cp->cp_pbdir &= ~0x06;
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cp->cp_pbodr &= ~0x06;
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#elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
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/*
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* Standard configuration for SCC's is on Part A
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*/
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ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
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ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
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ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
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#else
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/*
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* The IP860 has SCC3 and SCC4 on Port D
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*/
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ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
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#endif
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/* Allocate space for two buffer descriptors in the DP ram.
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*/
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#ifdef CFG_ALLOC_DPRAM
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dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
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#else
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dpaddr = CPM_SERIAL_BASE ;
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#endif
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/* Enable SDMA.
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*/
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im->im_siu_conf.sc_sdcr = 0x0001;
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/* Set the physical address of the host memory buffers in
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* the buffer descriptors.
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*/
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rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
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rbdf->cbd_bufaddr = (uint) (rbdf+2);
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rbdf->cbd_sc = 0;
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tbdf = rbdf + 1;
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tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
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tbdf->cbd_sc = 0;
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/* Set up the baud rate generator.
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*/
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serial_setbrg ();
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/* Set up the uart parameters in the parameter ram.
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*/
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up->scc_genscc.scc_rbase = dpaddr;
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up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
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/* Initialize Tx/Rx parameters.
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*/
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
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up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
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up->scc_genscc.scc_mrblr = 1; /* Single character receive */
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up->scc_maxidl = 0; /* disable max idle */
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up->scc_brkcr = 1; /* send one break character on stop TX */
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up->scc_parec = 0;
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up->scc_frmec = 0;
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up->scc_nosec = 0;
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up->scc_brkec = 0;
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up->scc_uaddr1 = 0;
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up->scc_uaddr2 = 0;
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up->scc_toseq = 0;
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up->scc_char1 = 0x8000;
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up->scc_char2 = 0x8000;
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up->scc_char3 = 0x8000;
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up->scc_char4 = 0x8000;
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up->scc_char5 = 0x8000;
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up->scc_char6 = 0x8000;
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up->scc_char7 = 0x8000;
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up->scc_char8 = 0x8000;
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up->scc_rccm = 0xc0ff;
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/* Set low latency / small fifo.
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*/
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sp->scc_gsmrh = SCC_GSMRH_RFW;
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/* Set SCC(x) clock mode to 16x
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* See 8xx_io/commproc.c for details.
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*
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* Wire BRG1 to SCCn
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*/
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/* Set UART mode, clock divider 16 on Tx and Rx
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*/
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sp->scc_gsmrl |=
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(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
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sp->scc_psmr |= SCU_PSMR_CL;
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/* Mask all interrupts and remove anything pending.
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*/
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sp->scc_sccm = 0;
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sp->scc_scce = 0xffff;
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sp->scc_dsr = 0x7e7e;
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sp->scc_psmr = 0x3000;
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/* Make the first buffer the only buffer.
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*/
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tbdf->cbd_sc |= BD_SC_WRAP;
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rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
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/* Enable transmitter/receiver.
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*/
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sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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return (0);
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}
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void
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serial_setbrg (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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|
|
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
|
volatile cpm8xx_t *cp = &(im->im_cpm);
|
|
|
|
/* Set up the baud rate generator.
|
|
* See 8xx_io/commproc.c for details.
|
|
*
|
|
* Wire BRG1 to SCCx
|
|
*/
|
|
|
|
cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
|
|
/* no |= needed, since BRG1 is 000 */
|
|
|
|
cp->cp_brgc1 =
|
|
(((gd->cpu_clk / 16 / gd->baudrate)-1) << 1) | CPM_BRG_EN;
|
|
}
|
|
|
|
void
|
|
serial_putc(const char c)
|
|
{
|
|
volatile cbd_t *tbdf;
|
|
volatile char *buf;
|
|
volatile scc_uart_t *up;
|
|
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
|
volatile cpm8xx_t *cpmp = &(im->im_cpm);
|
|
|
|
if (c == '\n')
|
|
serial_putc ('\r');
|
|
|
|
up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
|
|
|
|
tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
|
|
|
|
/* Wait for last character to go.
|
|
*/
|
|
|
|
buf = (char *)tbdf->cbd_bufaddr;
|
|
#if 0
|
|
__asm__("eieio");
|
|
while (tbdf->cbd_sc & BD_SC_READY)
|
|
__asm__("eieio");
|
|
#endif
|
|
|
|
*buf = c;
|
|
tbdf->cbd_datlen = 1;
|
|
tbdf->cbd_sc |= BD_SC_READY;
|
|
__asm__("eieio");
|
|
#if 1
|
|
while (tbdf->cbd_sc & BD_SC_READY)
|
|
__asm__("eieio");
|
|
#endif
|
|
}
|
|
|
|
int
|
|
serial_getc(void)
|
|
{
|
|
volatile cbd_t *rbdf;
|
|
volatile unsigned char *buf;
|
|
volatile scc_uart_t *up;
|
|
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
|
volatile cpm8xx_t *cpmp = &(im->im_cpm);
|
|
unsigned char c;
|
|
|
|
up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
|
|
|
|
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
|
|
|
|
/* Wait for character to show up.
|
|
*/
|
|
buf = (unsigned char *)rbdf->cbd_bufaddr;
|
|
while (rbdf->cbd_sc & BD_SC_EMPTY)
|
|
;
|
|
c = *buf;
|
|
rbdf->cbd_sc |= BD_SC_EMPTY;
|
|
|
|
return(c);
|
|
}
|
|
|
|
int
|
|
serial_tstc()
|
|
{
|
|
volatile cbd_t *rbdf;
|
|
volatile scc_uart_t *up;
|
|
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
|
volatile cpm8xx_t *cpmp = &(im->im_cpm);
|
|
|
|
up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
|
|
|
|
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
|
|
|
|
return(!(rbdf->cbd_sc & BD_SC_EMPTY));
|
|
}
|
|
|
|
#endif /* CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
|
|
|
|
|
|
void
|
|
serial_puts (const char *s)
|
|
{
|
|
while (*s) {
|
|
serial_putc (*s++);
|
|
}
|
|
}
|
|
|
|
|
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
|
|
|
void
|
|
kgdb_serial_init(void)
|
|
{
|
|
#if defined(CONFIG_8xx_CONS_SMC1)
|
|
serial_printf("[on SMC1] ");
|
|
#elif defined(CONFIG_8xx_CONS_SMC2)
|
|
serial_printf("[on SMC2] ");
|
|
#elif defined(CONFIG_8xx_CONS_SCC1)
|
|
serial_printf("[on SCC1] ");
|
|
#elif defined(CONFIG_8xx_CONS_SCC2)
|
|
serial_printf("[on SCC2] ");
|
|
#elif defined(CONFIG_8xx_CONS_SCC3)
|
|
serial_printf("[on SCC3] ");
|
|
#elif defined(CONFIG_8xx_CONS_SCC4)
|
|
serial_printf("[on SCC4] ");
|
|
#endif
|
|
}
|
|
|
|
void
|
|
putDebugChar (int c)
|
|
{
|
|
serial_putc (c);
|
|
}
|
|
|
|
void
|
|
putDebugStr (const char *str)
|
|
{
|
|
serial_puts (str);
|
|
}
|
|
|
|
int
|
|
getDebugChar (void)
|
|
{
|
|
return serial_getc();
|
|
}
|
|
|
|
void
|
|
kgdb_interruptible (int yes)
|
|
{
|
|
return;
|
|
}
|
|
#endif /* CFG_CMD_KGDB */
|
|
|
|
#endif /* CONFIG_8xx_CONS_NONE */
|
|
|