upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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525 lines
17 KiB
525 lines
17 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* defines for Cogent Motherboards
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*/
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#ifndef _COGENT_MB_H
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#define _COGENT_MB_H
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/*
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* Cogent Motherboard Address Map
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*
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* The size of a Cogent motherboard address space is 256 Mbytes (i.e. 28 bits).
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*
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* The first 32 Mbyte (0x0000000-0x1FFFFFF) is usually RAM. The following
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* 3 x 32 Mbyte areas (0x2000000-0x3FFFFFF, 0x4000000-0x5FFFFFF and
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* 0x6000000-0x7FFFFFF) are general I/O "slots" (slots 1, 2 and 3).
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* Most other motherboard devices have registers mapped into the area
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* 0xE000000-0xFFFFFFF (Motherboard I/O slot?). The area 0x8000000-0xDFFFFFF
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* is free for whatever.
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*
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* The location of the motherboard address space in the physical address space
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* of the cpu is given by CMA_MB_BASE. This value is determined by the cpu
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* module plugged into the motherboard and is configured above.
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*
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* Motherboard I/O devices mapped into the area (0xE000000-0xFFFFFFF)
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* generally only use byte lane 0 (D0-7) for their transfers, i.e. only
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* 8 bit, or 1 byte, transfers can take place, so all the registers are
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* only 8 bits wide. The exceptions are the motherboard flash, which uses
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* byte lanes 0 and 1 (i.e. 16 bits), and the mapped PCI address space.
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*
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* I/O registers within the mapped motherboard devices are 64 bit aligned
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* i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register
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* will be at byte 7 (the address + 7). For little endian addressing, the
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* register will be at byte 0 (the address + 0). To learn the endianess
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* we must include <asm/byteorder.h>
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*
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* Take the CMA102 and CMA111 motherboards as examples...
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*
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* The CMA102 has three CMABus I/O Expansion slots and no PCI bridge. The 3
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* CMABus slots are each mapped directly onto the three general I/O slots.
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*
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* The CMA111 has only one CMABus I/O Expansion slot, but has a V360EPC PCI
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* bridge. The CMABus slot is mapped onto general I/O slot 1. The standard
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* PCI Bus space is mapped onto general I/O slot 2, with a small area at the
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* top reserved for access to the V360EPC registers (0x5FF0000-0x5FFFFFF).
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* I/O slot 3 is unused. The extended PCI Bus space is mapped onto the area
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* 0xA000000-0xDFFFFFF.
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*/
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#define CMA_MB_RAM_BASE (CFG_CMA_MB_BASE+0x0000000)
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#define CMA_MB_RAM_SIZE 0x2000000 /* dip sws set actual size */
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#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1)
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#define CMA_MB_SLOT1_BASE (CFG_CMA_MB_BASE+0x2000000)
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#define CMA_MB_SLOT1_SIZE 0x2000000
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
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#define CMA_MB_SLOT2_BASE (CFG_CMA_MB_BASE+0x4000000)
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#define CMA_MB_SLOT2_SIZE 0x2000000
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
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#define CMA_MB_STDPCI_BASE (CFG_CMA_MB_BASE+0x4000000)
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#define CMA_MB_STDPCI_SIZE 0x1ff0000
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#define CMA_MB_V360EPC_BASE (CFG_CMA_MB_BASE+0x5ff0000)
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#define CMA_MB_V360EPC_SIZE 0x10000
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
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#define CMA_MB_SLOT3_BASE (CFG_CMA_MB_BASE+0x6000000)
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#define CMA_MB_SLOT3_SIZE 0x2000000
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT)
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#define CMA_MB_EXTPCI_BASE (CFG_CMA_MB_BASE+0xa000000)
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#define CMA_MB_EXTPCI_SIZE 0x4000000
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#endif
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#define CMA_MB_ROMLOW_BASE (CFG_CMA_MB_BASE+0xe000000)
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#define CMA_MB_ROMLOW_SIZE 0x800000
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#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
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#define CMA_MB_FLLOW_EXEC_BASE (CFG_CMA_MB_BASE+0xe000000)
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#define CMA_MB_FLLOW_EXEC_SIZE 0x100000
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#define CMA_MB_FLLOW_RDWR_BASE (CFG_CMA_MB_BASE+0xe400000)
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#define CMA_MB_FLLOW_RDWR_SIZE 0x400000
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
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#define CMA_MB_RTC_BASE (CFG_CMA_MB_BASE+0xe800000)
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#define CMA_MB_RTC_SIZE 0x4000
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
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#define CMA_MB_SERPAR_BASE (CFG_CMA_MB_BASE+0xe900000)
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#define CMA_MB_SERIALB_BASE (CMA_MB_SERPAR_BASE+0x00)
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#define CMA_MB_SERIALA_BASE (CMA_MB_SERPAR_BASE+0x40)
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#define CMA_MB_PARALLEL_BASE (CMA_MB_SERPAR_BASE+0x80)
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#define CMA_MB_SERPAR_SIZE 0xa0
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_KBM)
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#define CMA_MB_PKBM_BASE (CFG_CMA_MB_BASE+0xe900100)
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#define CMA_MB_PKBM_SIZE 0x10
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
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#define CMA_MB_LCD_BASE (CFG_CMA_MB_BASE+0xeb00000)
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#define CMA_MB_LCD_SIZE 0x10
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#endif
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#define CMA_MB_DIPSW_BASE (CFG_CMA_MB_BASE+0xec00000)
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#define CMA_MB_DIPSW_SIZE 0x10
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#if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM))
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#define CMA_MB_SLOT1CFG_BASE (CFG_CMA_MB_BASE+0xf100000)
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#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
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#define CMA_MB_SER2_BASE (CMA_MB_SLOT1CFG_BASE+0x80)
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#define CMA_MB_SER2B_BASE (CMA_MB_SER2_BASE+0x00)
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#define CMA_MB_SER2A_BASE (CMA_MB_SER2_BASE+0x40)
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#endif
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#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT1)
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#define CMA_MB_S1KBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200)
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) && !defined(COGENT_CMA150)
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#define CMA_MB_IREQ1STAT_BASE (CMA_MB_SLOT1CFG_BASE+0x100)
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#define CMA_MB_AKBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200)
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#define CMA_MB_IREQ1MASK_BASE (CMA_MB_SLOT1CFG_BASE+0x300)
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#endif
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#define CMA_MB_SLOT1CFG_SIZE 0x400
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
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#define CMA_MB_SLOT2CFG_BASE (CFG_CMA_MB_BASE+0xf200000)
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#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2)
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#define CMA_MB_S2KBM_BASE (CMA_MB_SLOT2CFG_BASE+0x200)
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#endif
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#define CMA_MB_SLOT2CFG_SIZE 0x400
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
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#define CMA_MB_PCICTL_BASE (CFG_CMA_MB_BASE+0xf200000)
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#define CMA_MB_PCI_V3CTL_BASE (CMA_MB_PCICTL_BASE+0x100)
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#define CMA_MB_PCI_IDSEL_BASE (CMA_MB_PCICTL_BASE+0x200)
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#define CMA_MB_PCI_IMASK_BASE (CMA_MB_PCICTL_BASE+0x300)
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#define CMA_MB_PCI_ISTAT_BASE (CMA_MB_PCICTL_BASE+0x400)
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#define CMA_MB_PCI_MBID_BASE (CMA_MB_PCICTL_BASE+0x500)
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#define CMA_MB_PCI_MBREV_BASE (CMA_MB_PCICTL_BASE+0x600)
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#define CMA_MB_PCICTL_SIZE 0x700
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
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#define CMA_MB_SLOT3CFG_BASE (CFG_CMA_MB_BASE+0xf300000)
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#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3)
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#define CMA_MB_S3KBM_BASE (CMA_MB_SLOT3CFG_BASE+0x200)
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#endif
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#define CMA_MB_SLOT3CFG_SIZE 0x400
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#endif
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#define CMA_MB_ROMHIGH_BASE (CFG_CMA_MB_BASE+0xf800000)
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#define CMA_MB_ROMHIGH_SIZE 0x800000
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#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
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#define CMA_MB_FLHIGH_EXEC_BASE (CFG_CMA_MB_BASE+0xf800000)
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#define CMA_MB_FLHIGH_EXEC_SIZE 0x100000
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#define CMA_MB_FLHIGH_RDWR_BASE (CFG_CMA_MB_BASE+0xfc00000)
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#define CMA_MB_FLHIGH_RDWR_SIZE 0x400000
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
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/* PCI Control Register bits */
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/* V360EPC Control register bits */
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#define CMA_MB_PCI_V3CTL_RESET 0x01
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#define CMA_MB_PCI_V3CTL_EXTADD 0x08
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/* PCI ID Select register bits */
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#define CMA_MB_PCI_IDSEL_SLOTA 0x01
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#define CMA_MB_PCI_IDSEL_SLOTB 0x02
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#define CMA_MB_PCI_IDSEL_GD82559 0x04
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#define CMA_MB_PCI_IDSEL_B69000 0x08
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#define CMA_MB_PCI_IDSEL_PD6832 0x10
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/* PCI Interrupt Mask/Status register bits */
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#define CMA_MB_PCI_IMS_INTA 0x01
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#define CMA_MB_PCI_IMS_INTB 0x02
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#define CMA_MB_PCI_IMS_INTC 0x04
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#define CMA_MB_PCI_IMS_INTD 0x08
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#define CMA_MB_PCI_IMS_CBINT 0x10
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#define CMA_MB_PCI_IMS_V3LINT 0x80
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#endif
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#if (CMA_MB_CAPS & (CMA_MB_CAP_KBM|CMA_MB_CAP_SER2)) && !defined(COGENT_CMA150)
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/*
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* IREQ1 Interrupt Mask/Status register bits
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* (Note: not available on CMA150 - must poll HT6542B interrupt register)
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*/
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#define IREQ1_MINT 0x01
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#define IREQ1_KINT 0x02
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#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
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#define IREQ1_SINT2 0x04
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#define IREQ1_SINT3 0x08
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#endif
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#endif
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#ifndef __ASSEMBLY__
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#include <asm/byteorder.h>
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/* a single CMA10x motherboard i/o register */
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typedef
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struct {
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#if defined(__LITTLE_ENDIAN)
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unsigned char value;
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#endif
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unsigned char filler[7];
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#if defined(__BIG_ENDIAN)
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unsigned char value;
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#endif
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}
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cma_mb_reg;
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extern __inline__ unsigned char
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cma_mb_reg_read(volatile cma_mb_reg *reg)
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{
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unsigned char data = reg->value;
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__asm__ __volatile__ ("eieio" : : : "memory");
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return data;
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}
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extern __inline__ void
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cma_mb_reg_write(volatile cma_mb_reg *reg, unsigned char data)
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{
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reg->value = data;
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__asm__ __volatile__ ("eieio" : : : "memory");
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}
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#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
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/* MK48T02 RTC registers */
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typedef
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struct {
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cma_mb_reg sram[2040];/* Battery-Backed SRAM */
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cma_mb_reg clk_ctl; /* Clock Control Register */
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cma_mb_reg clk_sec; /* Clock Seconds Register */
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cma_mb_reg clk_min; /* Clock Minutes Register */
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cma_mb_reg clk_hour; /* Clock Hour Register */
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cma_mb_reg clk_day; /* Clock Day Register */
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cma_mb_reg clk_date; /* Clock Date Register */
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cma_mb_reg clk_month; /* Clock Month Register */
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cma_mb_reg clk_year; /* Clock Year Register */
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}
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cma_mb_rtc;
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
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/* ST16C522 Serial I/O */
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typedef
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struct {
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cma_mb_reg ser_rhr; /* Receive Holding Register (R, DLAB=0) */
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cma_mb_reg ser_ier; /* Interrupt Enable Register (R/W, DLAB=0) */
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cma_mb_reg ser_isr; /* Interrupt Status Register (R) */
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cma_mb_reg ser_lcr; /* Line Control Register (R/W) */
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cma_mb_reg ser_mcr; /* Modem Control Register (R/W) */
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cma_mb_reg ser_lsr; /* Line Status Register (R) */
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cma_mb_reg ser_msr; /* Modem Status Register (R/W) */
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cma_mb_reg ser_spr; /* Scratch Pad Register (R/W) */
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}
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cma_mb_serial;
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#define ser_thr ser_rhr /* Transmit Holding Register (W, DLAB=0) */
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#define ser_brl ser_rhr /* Baud Rate Divisor Low Byte (R/W, DLAB=1) */
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#define ser_brh ser_ier /* Baud Rate Divisor High Byte (R/W, DLAB=1) */
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#define ser_fcr ser_isr /* FIFO Control Register (W) */
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#define ser_nop ser_lsr /* No Operation (W) */
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/* ST16C522 Parallel I/O */
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typedef
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struct {
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cma_mb_reg par_rdr; /* Port Read Data Register (R) */
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cma_mb_reg par_sr; /* Status Register (R) */
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cma_mb_reg par_cmd; /* Command Register (R) */
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}
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cma_mb_parallel;
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#define par_wdr par_rdr /* Port Write Data Register (W) */
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#define par_ios par_sr /* I/O Select Register (W) */
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#define par_ctl par_cmd /* Control Register (W) */
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302)
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/* HT6542B PS/2 Keyboard/Mouse Controller */
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typedef
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struct {
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cma_mb_reg kbm_rdr; /* Read Data Register (R) */
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cma_mb_reg kbm_sr; /* Status Register (R) */
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}
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cma_mb_kbm;
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#define kbm_wdr kbm_rdr /* Write Data Register (W) */
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#define kbm_cmd kbm_sr /* Command Register (W) */
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#endif
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#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
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/* HD44780 LCD Display */
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typedef
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struct {
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cma_mb_reg lcd_ccr; /* Current Character Register (R/W) */
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cma_mb_reg lcd_bsr; /* Busy Status Register (R) */
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}
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cma_mb_lcd;
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#define lcd_cmd lcd_bsr /* Command Register (W) */
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#endif
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/* 8-Position Configuration Switch */
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typedef
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struct {
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cma_mb_reg dip_val; /* Dip Switch value (R) */
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}
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cma_mb_dipsw;
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#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
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/* V360EPC PCI Bridge */
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typedef
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struct {
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#if defined(__LITTLE_ENDIAN)
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unsigned short v3_pci_vendor; /* 0x00 */
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unsigned short v3_pci_device;
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unsigned short v3_pci_cmd; /* 0x04 */
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unsigned short v3_pci_stat;
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unsigned long v3_pci_cc_rev; /* 0x08 */
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unsigned long v3_pci_hdr_cfg; /* 0x0c */
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unsigned long v3_pci_io_base; /* 0x10 */
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unsigned long v3_pci_base0; /* 0x14 */
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unsigned long v3_pci_base1; /* 0x18 */
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unsigned long reserved1[4]; /* 0x1c */
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unsigned short v3_pci_sub_vendor; /* 0x2c */
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unsigned short v3_pci_sub_id;
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unsigned long v3_pci_rom; /* 0x30 */
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unsigned long reserved2[2]; /* 0x34 */
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unsigned long v3_pci_bparam; /* 0x3c */
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unsigned long v3_pci_map0; /* 0x40 */
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unsigned long v3_pci_map1; /* 0x44 */
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unsigned long v3_pci_int_stat; /* 0x48 */
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unsigned long v3_pci_int_cfg; /* 0x4c */
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unsigned long reserved3[1]; /* 0x50 */
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unsigned long v3_lb_base0; /* 0x54 */
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unsigned long v3_lb_base1; /* 0x58 */
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unsigned short reserved4; /* 0x5c */
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unsigned short v3_lb_map0;
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unsigned short reserved5; /* 0x60 */
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unsigned short v3_lb_map1;
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unsigned short v3_lb_base2; /* 0x64 */
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unsigned short v3_lb_map2;
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unsigned long v3_lb_size; /* 0x68 */
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unsigned short reserved6; /* 0x6c */
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unsigned short v3_lb_io_base;
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unsigned short v3_fifo_cfg; /* 0x70 */
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unsigned short v3_fifo_priority;
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unsigned short v3_fifo_stat; /* 0x74 */
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unsigned char v3_lb_istat;
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unsigned char v3_lb_imask;
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unsigned short v3_system; /* 0x78 */
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unsigned short v3_lb_cfg;
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unsigned short v3_pci_cfg; /* 0x7c */
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unsigned short reserved7;
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unsigned long v3_dma_pci_addr0; /* 0x80 */
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unsigned long v3_dma_local_addr0; /* 0x84 */
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unsigned long v3_dma_length0:24; /* 0x88 */
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unsigned long v3_dma_csr0:8;
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unsigned long v3_dma_ctlb_adr0; /* 0x8c */
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unsigned long v3_dma_pci_addr1; /* 0x90 */
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unsigned long v3_dma_local_addr1; /* 0x94 */
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unsigned long v3_dma_length1:24; /* 0x98 */
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unsigned long v3_dma_csr1:8;
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unsigned long v3_dma_ctlb_adr1; /* 0x9c */
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unsigned long v3_i20_mups[8]; /* 0xa0 */
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unsigned char v3_mail_data0; /* 0xc0 */
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unsigned char v3_mail_data1;
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unsigned char v3_mail_data2;
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unsigned char v3_mail_data3;
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unsigned char v3_mail_data4; /* 0xc4 */
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unsigned char v3_mail_data5;
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unsigned char v3_mail_data6;
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unsigned char v3_mail_data7;
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unsigned char v3_mail_data8; /* 0xc8 */
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unsigned char v3_mail_data9;
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unsigned char v3_mail_data10;
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unsigned char v3_mail_data11;
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unsigned char v3_mail_data12; /* 0xcc */
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unsigned char v3_mail_data13;
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unsigned char v3_mail_data14;
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unsigned char v3_mail_data15;
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unsigned short v3_pci_mail_iewr; /* 0xd0 */
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unsigned short v3_pci_mail_ierd;
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unsigned short v3_lb_mail_iewr; /* 0xd4 */
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unsigned short v3_lb_mail_ierd;
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unsigned short v3_mail_wr_stat; /* 0xd8 */
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unsigned short v3_mail_rd_stat;
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unsigned long v3_qba_map; /* 0xdc */
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unsigned long v3_dma_delay:8; /* 0xe0 */
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unsigned long reserved8:24;
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unsigned long reserved9[7]; /* 0xe4 */
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#endif
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#if defined(__BIG_ENDIAN)
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unsigned short v3_pci_device; /* 0x00 */
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unsigned short v3_pci_vendor;
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unsigned short v3_pci_stat; /* 0x04 */
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unsigned short v3_pci_cmd;
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unsigned long v3_pci_cc_rev; /* 0x08 */
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unsigned long v3_pci_hdr_cfg; /* 0x0c */
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unsigned long v3_pci_io_base; /* 0x10 */
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unsigned long v3_pci_base0; /* 0x14 */
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unsigned long v3_pci_base1; /* 0x18 */
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unsigned long reserved1[4]; /* 0x1c */
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unsigned short v3_pci_sub_id; /* 0x2c */
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unsigned short v3_pci_sub_vendor;
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unsigned long v3_pci_rom; /* 0x30 */
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unsigned long reserved2[2]; /* 0x34 */
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unsigned long v3_pci_bparam; /* 0x3c */
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unsigned long v3_pci_map0; /* 0x40 */
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unsigned long v3_pci_map1; /* 0x44 */
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unsigned long v3_pci_int_stat; /* 0x48 */
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unsigned long v3_pci_int_cfg; /* 0x4c */
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unsigned long reserved3; /* 0x50 */
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unsigned long v3_lb_base0; /* 0x54 */
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unsigned long v3_lb_base1; /* 0x58 */
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unsigned short v3_lb_map0; /* 0x5c */
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unsigned short reserved4;
|
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unsigned short v3_lb_map1; /* 0x60 */
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unsigned short reserved5;
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unsigned short v3_lb_map2; /* 0x64 */
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unsigned short v3_lb_base2;
|
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unsigned long v3_lb_size; /* 0x68 */
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unsigned short v3_lb_io_base; /* 0x6c */
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unsigned short reserved6;
|
|
unsigned short v3_fifo_priority; /* 0x70 */
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unsigned short v3_fifo_cfg;
|
|
unsigned char v3_lb_imask; /* 0x74 */
|
|
unsigned char v3_lb_istat;
|
|
unsigned short v3_fifo_stat;
|
|
unsigned short v3_lb_cfg; /* 0x78 */
|
|
unsigned short v3_system;
|
|
unsigned short reserved7; /* 0x7c */
|
|
unsigned short v3_pci_cfg;
|
|
unsigned long v3_dma_pci_addr0; /* 0x80 */
|
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unsigned long v3_dma_local_addr0; /* 0x84 */
|
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unsigned long v3_dma_csr0:8; /* 0x88 */
|
|
unsigned long v3_dma_length0:24;
|
|
unsigned long v3_dma_ctlb_adr0; /* 0x8c */
|
|
unsigned long v3_dma_pci_addr1; /* 0x90 */
|
|
unsigned long v3_dma_local_addr1; /* 0x94 */
|
|
unsigned long v3_dma_csr1:8; /* 0x98 */
|
|
unsigned long v3_dma_length1:24;
|
|
unsigned long v3_dma_ctlb_adr1; /* 0x9c */
|
|
unsigned long v3_i20_mups[8]; /* 0xa0 */
|
|
unsigned char v3_mail_data3; /* 0xc0 */
|
|
unsigned char v3_mail_data2;
|
|
unsigned char v3_mail_data1;
|
|
unsigned char v3_mail_data0;
|
|
unsigned char v3_mail_data7; /* 0xc4 */
|
|
unsigned char v3_mail_data6;
|
|
unsigned char v3_mail_data5;
|
|
unsigned char v3_mail_data4;
|
|
unsigned char v3_mail_data11; /* 0xc8 */
|
|
unsigned char v3_mail_data10;
|
|
unsigned char v3_mail_data9;
|
|
unsigned char v3_mail_data8;
|
|
unsigned char v3_mail_data15; /* 0xcc */
|
|
unsigned char v3_mail_data14;
|
|
unsigned char v3_mail_data13;
|
|
unsigned char v3_mail_data12;
|
|
unsigned short v3_pci_mail_ierd; /* 0xd0 */
|
|
unsigned short v3_pci_mail_iewr;
|
|
unsigned short v3_lb_mail_ierd; /* 0xd4 */
|
|
unsigned short v3_lb_mail_iewr;
|
|
unsigned short v3_mail_rd_stat; /* 0xd8 */
|
|
unsigned short v3_mail_wr_stat;
|
|
unsigned long v3_qba_map; /* 0xdc */
|
|
unsigned long reserved8:24; /* 0xe0 */
|
|
unsigned long v3_dma_delay:8;
|
|
unsigned long reserved9[7]; /* 0xe4 */
|
|
#endif
|
|
} /* 0x100 */
|
|
cma_mb_v360epc;
|
|
|
|
#endif
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* _COGENT_MB_H */
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