upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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50 lines
1.5 KiB
50 lines
1.5 KiB
/*
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* CPU specific interrupt routine */
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#include <common.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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int interrupt_init(void)
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{
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int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
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/* Make sure all interrupts are disabled */
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setbits_be32(&intp->imrl0, 0x1);
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enable_interrupts();
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return 0;
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}
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#if defined(CONFIG_MCFTMR)
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void dtimer_intr_setup(void)
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{
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int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
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out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
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clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
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clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
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}
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#endif
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