upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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862 lines
24 KiB
862 lines
24 KiB
/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Based on original work by
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* Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
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* Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
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* modifications for the cpci750 by reinhard.arlt@esd-electronics.com
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* modifications for the P3M750 by roel.loeffen@prodrive.nl
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*/
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/*
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* p3m750.c - main board support/init for the Prodrive p3m750/p3m7448.
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*/
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#include <common.h>
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#include <74xx_7xx.h>
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#include "../../Marvell/include/memory.h"
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#include "../../Marvell/include/pci.h"
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#include "../../Marvell/include/mv_gen_reg.h"
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#include <net.h>
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#include <i2c.h>
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#include "eth.h"
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#include "mpsc.h"
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#include "64460.h"
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#include "mv_regs.h"
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#include "p3mx.h"
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DECLARE_GLOBAL_DATA_PTR;
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#undef DEBUG
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/*#define DEBUG */
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#ifdef CONFIG_PCI
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#define MAP_PCI
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#endif /* of CONFIG_PCI */
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#ifdef DEBUG
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#define DP(x) x
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#else
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#define DP(x)
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#endif
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extern flash_info_t flash_info[];
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/* ------------------------------------------------------------------------- */
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/* this is the current GT register space location */
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/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
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/* Unfortunately, we cant change it while we are in flash, so we initialize it
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* to the "final" value. This means that any debug_led calls before
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* board_early_init_f wont work right (like in cpu_init_f).
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* See also my_remap_gt_regs below. (NTL)
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*/
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void board_prebootm_init (void);
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unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
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int display_mem_map (void);
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void set_led(int);
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/* ------------------------------------------------------------------------- */
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/*
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* This is a version of the GT register space remapping function that
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* doesn't touch globals (meaning, it's ok to run from flash.)
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*
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* Unfortunately, this has the side effect that a writable
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* INTERNAL_REG_BASE_ADDR is impossible. Oh well.
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*/
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void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
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{
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u32 temp;
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/* check and see if it's already moved */
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temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
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if ((temp & 0xffff) == new_loc >> 16)
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return;
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temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
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0xffff0000) | (new_loc >> 16);
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out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
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while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
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}
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#ifdef CONFIG_PCI
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static void gt_pci_config (void)
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{
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unsigned int stat;
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unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, */
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/* FuncNum 10:8, RegNum 7:2 */
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/*
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* In PCIX mode devices provide their own bus and device numbers.
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* We query the Discovery II's
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* config registers by writing ones to the bus and device.
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* We then update the Virtual register with the correct value for the
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* bus and device.
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*/
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if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
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GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
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GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
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GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
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GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
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(stat & 0xffff0000) | CFG_PCI_IDSEL);
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}
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if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
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GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
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GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
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GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
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GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
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(stat & 0xffff0000) | CFG_PCI_IDSEL);
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}
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/* Enable master */
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PCI_MASTER_ENABLE (0, SELF);
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PCI_MASTER_ENABLE (1, SELF);
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/* Enable PCI0/1 Mem0 and IO 0 disable all others */
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GT_REG_READ (BASE_ADDR_ENABLE, &stat);
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stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) |
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(1 << 18);
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stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
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GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
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/* ronen:
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* add write to pci remap registers for 64460.
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* in 64360 when writing to pci base go and overide remap automaticaly,
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* in 64460 it doesn't
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*/
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GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
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GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
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GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
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GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
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GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
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GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
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GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
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GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
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GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
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GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
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GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
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GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
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/* PCI interface settings */
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/* Timeout set to retry forever */
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GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
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GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
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/* ronen - enable only CS0 and Internal reg!! */
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GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
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GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
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/* ronen:
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* update the pci internal registers base address.
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*/
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#ifdef MAP_PCI
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for (stat = 0; stat <= PCI_HOST1; stat++)
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pciWriteConfigReg (stat,
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PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
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SELF, CFG_GT_REGS);
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#endif
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}
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#endif
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/* Setup CPU interface paramaters */
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static void gt_cpu_config (void)
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{
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cpu_t cpu = get_cpu_type ();
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ulong tmp;
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/* cpu configuration register */
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tmp = GTREGREAD (CPU_CONFIGURATION);
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/* set the SINGLE_CPU bit see MV64460 */
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#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
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tmp |= CPU_CONF_SINGLE_CPU;
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#endif
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tmp &= ~CPU_CONF_AACK_DELAY_2;
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tmp |= CPU_CONF_DP_VALID;
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tmp |= CPU_CONF_AP_VALID;
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tmp |= CPU_CONF_PIPELINE;
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GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
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/* CPU master control register */
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tmp = GTREGREAD (CPU_MASTER_CONTROL);
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tmp |= CPU_MAST_CTL_ARB_EN;
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if ((cpu == CPU_7400) ||
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(cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
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tmp |= CPU_MAST_CTL_CLEAN_BLK;
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tmp |= CPU_MAST_CTL_FLUSH_BLK;
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} else {
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/* cleanblock must be cleared for CPUs
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* that do not support this command (603e, 750)
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* see Res#1 */
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tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
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tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
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}
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GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
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}
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/*
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* board_early_init_f.
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*
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* set up gal. device mappings, etc.
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*/
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int board_early_init_f (void)
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{
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/* set up the GT the way the kernel wants it
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* the call to move the GT register space will obviously
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* fail if it has already been done, but we're going to assume
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* that if it's not at the power-on location, it's where we put
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* it last time. (huber)
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*/
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my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
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#ifdef CONFIG_PCI
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gt_pci_config ();
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#endif
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/* mask all external interrupt sources */
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GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
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GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
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/* new in >MV6436x */
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GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
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GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
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/* --------------------- */
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GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
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GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
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GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
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GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
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/* Device and Boot bus settings
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*/
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memoryMapDeviceSpace(DEVICE0, 0, 0);
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GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0);
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memoryMapDeviceSpace(DEVICE1, 0, 0);
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GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0);
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memoryMapDeviceSpace(DEVICE2, 0, 0);
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GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0);
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memoryMapDeviceSpace(DEVICE3, 0, 0);
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GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
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GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_BOOT_PAR);
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gt_cpu_config();
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/* MPP setup */
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GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
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GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
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GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
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GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
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GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
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set_led(LED_RED);
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return 0;
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}
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/* various things to do after relocation */
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int misc_init_r ()
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{
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u8 val;
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icache_enable ();
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#ifdef CFG_L2
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l2cache_enable ();
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#endif
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#ifdef CONFIG_MPSC
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mpsc_sdma_init ();
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mpsc_init2 ();
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#endif
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/*
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* Enable trickle changing in RTC upon powerup
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* No diode, 250 ohm series resistor
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*/
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val = 0xa5;
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i2c_write(CFG_I2C_RTC_ADDR, 8, 1, &val, 1);
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return 0;
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}
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int board_early_init_r(void)
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{
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/* now relocate the debug serial driver */
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mpsc_putchar += gd->reloc_off;
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mpsc_getchar += gd->reloc_off;
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mpsc_test_char += gd->reloc_off;
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return 0;
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}
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void after_reloc (ulong dest_addr, gd_t * gd)
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{
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memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
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/* display_mem_map(); */
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/* now, jump to the main U-Boot board init code */
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set_led(LED_GREEN);
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board_init_r (gd, dest_addr);
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/* NOTREACHED */
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}
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/*
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* Check Board Identity:
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* right now, assume borad type. (there is just one...after all)
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*/
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int checkboard (void)
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{
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char *s = getenv("serial#");
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printf("Board: %s", CFG_BOARD_NAME);
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return (0);
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}
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void set_led(int col)
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{
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int tmp;
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int on_pin;
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int off_pin;
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/* Program Mpp[22] as Gpp[22]
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* Program Mpp[23] as Gpp[23]
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*/
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tmp = GTREGREAD(MPP_CONTROL2);
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tmp &= 0x00ffffff;
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GT_REG_WRITE(MPP_CONTROL2,tmp);
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/* Program Gpp[22] and Gpp[23] as output
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*/
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tmp = GTREGREAD(GPP_IO_CONTROL);
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tmp |= 0x00C00000;
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GT_REG_WRITE(GPP_IO_CONTROL, tmp);
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/* Program Gpp[22] and Gpp[23] as active high
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*/
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tmp = GTREGREAD(GPP_LEVEL_CONTROL);
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tmp &= 0xff3fffff;
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GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);
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switch(col) {
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default:
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case LED_OFF :
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on_pin = 0;
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off_pin = ((1 << 23) | (1 << 22));
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break;
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case LED_RED :
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on_pin = (1 << 23);
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off_pin = (1 << 22);
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break;
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case LED_GREEN :
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on_pin = (1 << 22);
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off_pin = (1 << 23);
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break;
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case LED_ORANGE :
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on_pin = ((1 << 23) | (1 << 22));
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off_pin = 0;
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break;
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}
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/* Set output Gpp[22] and Gpp[23]
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*/
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tmp = GTREGREAD(GPP_VALUE);
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tmp |= on_pin;
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tmp &= ~off_pin;
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GT_REG_WRITE(GPP_VALUE, tmp);
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}
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int display_mem_map (void)
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{
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int i;
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unsigned int base, size, width;
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#ifdef CONFIG_PCI
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int j;
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#endif
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/* SDRAM */
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printf ("SD (DDR) RAM\n");
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for (i = 0; i <= BANK3; i++) {
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base = memoryGetBankBaseAddress (i);
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size = memoryGetBankSize (i);
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if (size != 0)
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printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
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i, base, size >> 20);
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}
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#ifdef CONFIG_PCI
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/* CPU's PCI windows */
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for (i = 0; i <= PCI_HOST1; i++) {
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printf ("\nCPU's PCI %d windows\n", i);
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base = pciGetSpaceBase (i, PCI_IO);
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size = pciGetSpaceSize (i, PCI_IO);
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printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
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size >> 20);
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/* ronen currently only first PCI MEM is used 3 */
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for (j = 0; j <= PCI_REGION0; j++) {
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base = pciGetSpaceBase (i, j);
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size = pciGetSpaceSize (i, j);
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printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",
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j, base, size >> 20);
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}
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}
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#endif /* of CONFIG_PCI */
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/* Bootrom */
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base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
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size = memoryGetDeviceSize (BOOT_DEVICE);
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width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
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printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
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base, size >> 20, width);
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return (0);
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}
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/* DRAM check routines copied from gw8260 */
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#if defined (CFG_DRAM_TEST)
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/*********************************************************************/
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/* NAME: move64() - moves a double word (64-bit) */
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/* */
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/* DESCRIPTION: */
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/* this function performs a double word move from the data at */
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/* the source pointer to the location at the destination pointer. */
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/* */
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/* INPUTS: */
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/* unsigned long long *src - pointer to data to move */
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/* */
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/* OUTPUTS: */
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/* unsigned long long *dest - pointer to locate to move data */
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/* */
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/* RETURNS: */
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/* None */
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/* */
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/* RESTRICTIONS/LIMITATIONS: */
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/* May cloober fr0. */
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/* */
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/*********************************************************************/
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static void move64 (unsigned long long *src, unsigned long long *dest)
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{
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asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
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|
"stfd 0, 0(4)" /* *dest = fpr0 */
|
|
: : : "fr0"); /* Clobbers fr0 */
|
|
return;
|
|
}
|
|
|
|
|
|
#if defined (CFG_DRAM_TEST_DATA)
|
|
|
|
unsigned long long pattern[] = {
|
|
0xaaaaaaaaaaaaaaaaULL,
|
|
0xccccccccccccccccULL,
|
|
0xf0f0f0f0f0f0f0f0ULL,
|
|
0xff00ff00ff00ff00ULL,
|
|
0xffff0000ffff0000ULL,
|
|
0xffffffff00000000ULL,
|
|
0x00000000ffffffffULL,
|
|
0x0000ffff0000ffffULL,
|
|
0x00ff00ff00ff00ffULL,
|
|
0x0f0f0f0f0f0f0f0fULL,
|
|
0x3333333333333333ULL,
|
|
0x5555555555555555ULL
|
|
};
|
|
|
|
/*********************************************************************/
|
|
/* NAME: mem_test_data() - test data lines for shorts and opens */
|
|
/* */
|
|
/* DESCRIPTION: */
|
|
/* Tests data lines for shorts and opens by forcing adjacent data */
|
|
/* to opposite states. Because the data lines could be routed in */
|
|
/* an arbitrary manner the must ensure test patterns ensure that */
|
|
/* every case is tested. By using the following series of binary */
|
|
/* patterns every combination of adjacent bits is test regardless */
|
|
/* of routing. */
|
|
/* */
|
|
/* ...101010101010101010101010 */
|
|
/* ...110011001100110011001100 */
|
|
/* ...111100001111000011110000 */
|
|
/* ...111111110000000011111111 */
|
|
/* */
|
|
/* Carrying this out, gives us six hex patterns as follows: */
|
|
/* */
|
|
/* 0xaaaaaaaaaaaaaaaa */
|
|
/* 0xcccccccccccccccc */
|
|
/* 0xf0f0f0f0f0f0f0f0 */
|
|
/* 0xff00ff00ff00ff00 */
|
|
/* 0xffff0000ffff0000 */
|
|
/* 0xffffffff00000000 */
|
|
/* */
|
|
/* The number test patterns will always be given by: */
|
|
/* */
|
|
/* log(base 2)(number data bits) = log2 (64) = 6 */
|
|
/* */
|
|
/* To test for short and opens to other signals on our boards. we */
|
|
/* simply */
|
|
/* test with the 1's complemnt of the paterns as well. */
|
|
/* */
|
|
/* OUTPUTS: */
|
|
/* Displays failing test pattern */
|
|
/* */
|
|
/* RETURNS: */
|
|
/* 0 - Passed test */
|
|
/* 1 - Failed test */
|
|
/* */
|
|
/* RESTRICTIONS/LIMITATIONS: */
|
|
/* Assumes only one one SDRAM bank */
|
|
/* */
|
|
/*********************************************************************/
|
|
int mem_test_data (void)
|
|
{
|
|
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
|
|
unsigned long long temp64 = 0;
|
|
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
|
|
int i;
|
|
unsigned int hi, lo;
|
|
|
|
for (i = 0; i < num_patterns; i++) {
|
|
move64 (&(pattern[i]), pmem);
|
|
move64 (pmem, &temp64);
|
|
|
|
/* hi = (temp64>>32) & 0xffffffff; */
|
|
/* lo = temp64 & 0xffffffff; */
|
|
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
|
|
|
|
hi = (pattern[i] >> 32) & 0xffffffff;
|
|
lo = pattern[i] & 0xffffffff;
|
|
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
|
|
|
|
if (temp64 != pattern[i]) {
|
|
printf ("\n Data Test Failed, pattern 0x%08x%08x",
|
|
hi, lo);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CFG_DRAM_TEST_DATA */
|
|
|
|
#if defined (CFG_DRAM_TEST_ADDRESS)
|
|
/*********************************************************************/
|
|
/* NAME: mem_test_address() - test address lines */
|
|
/* */
|
|
/* DESCRIPTION: */
|
|
/* This function performs a test to verify that each word im */
|
|
/* memory is uniquly addressable. The test sequence is as follows: */
|
|
/* */
|
|
/* 1) write the address of each word to each word. */
|
|
/* 2) verify that each location equals its address */
|
|
/* */
|
|
/* OUTPUTS: */
|
|
/* Displays failing test pattern and address */
|
|
/* */
|
|
/* RETURNS: */
|
|
/* 0 - Passed test */
|
|
/* 1 - Failed test */
|
|
/* */
|
|
/* RESTRICTIONS/LIMITATIONS: */
|
|
/* */
|
|
/* */
|
|
/*********************************************************************/
|
|
int mem_test_address (void)
|
|
{
|
|
volatile unsigned int *pmem =
|
|
(volatile unsigned int *) CFG_MEMTEST_START;
|
|
const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
|
|
unsigned int i;
|
|
|
|
/* write address to each location */
|
|
for (i = 0; i < size; i++)
|
|
pmem[i] = i;
|
|
|
|
/* verify each loaction */
|
|
for (i = 0; i < size; i++) {
|
|
if (pmem[i] != i) {
|
|
printf ("\n Address Test Failed at 0x%x", i);
|
|
return 1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
#endif /* CFG_DRAM_TEST_ADDRESS */
|
|
|
|
#if defined (CFG_DRAM_TEST_WALK)
|
|
/*********************************************************************/
|
|
/* NAME: mem_march() - memory march */
|
|
/* */
|
|
/* DESCRIPTION: */
|
|
/* Marches up through memory. At each location verifies rmask if */
|
|
/* read = 1. At each location write wmask if write = 1. Displays */
|
|
/* failing address and pattern. */
|
|
/* */
|
|
/* INPUTS: */
|
|
/* volatile unsigned long long * base - start address of test */
|
|
/* unsigned int size - number of dwords(64-bit) to test */
|
|
/* unsigned long long rmask - read verify mask */
|
|
/* unsigned long long wmask - wrtie verify mask */
|
|
/* short read - verifies rmask if read = 1 */
|
|
/* short write - writes wmask if write = 1 */
|
|
/* */
|
|
/* OUTPUTS: */
|
|
/* Displays failing test pattern and address */
|
|
/* */
|
|
/* RETURNS: */
|
|
/* 0 - Passed test */
|
|
/* 1 - Failed test */
|
|
/* */
|
|
/* RESTRICTIONS/LIMITATIONS: */
|
|
/* */
|
|
/* */
|
|
/*********************************************************************/
|
|
int mem_march (volatile unsigned long long *base,
|
|
unsigned int size,
|
|
unsigned long long rmask,
|
|
unsigned long long wmask, short read, short write)
|
|
{
|
|
unsigned int i;
|
|
unsigned long long temp = 0;
|
|
unsigned int hitemp, lotemp, himask, lomask;
|
|
|
|
for (i = 0; i < size; i++) {
|
|
if (read != 0) {
|
|
/* temp = base[i]; */
|
|
move64 ((unsigned long long *) &(base[i]), &temp);
|
|
if (rmask != temp) {
|
|
hitemp = (temp >> 32) & 0xffffffff;
|
|
lotemp = temp & 0xffffffff;
|
|
himask = (rmask >> 32) & 0xffffffff;
|
|
lomask = rmask & 0xffffffff;
|
|
|
|
printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
|
|
return 1;
|
|
}
|
|
}
|
|
if (write != 0) {
|
|
/* base[i] = wmask; */
|
|
move64 (&wmask, (unsigned long long *) &(base[i]));
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
#endif /* CFG_DRAM_TEST_WALK */
|
|
|
|
/*********************************************************************/
|
|
/* NAME: mem_test_walk() - a simple walking ones test */
|
|
/* */
|
|
/* DESCRIPTION: */
|
|
/* Performs a walking ones through entire physical memory. The */
|
|
/* test uses as series of memory marches, mem_march(), to verify */
|
|
/* and write the test patterns to memory. The test sequence is as */
|
|
/* follows: */
|
|
/* 1) march writing 0000...0001 */
|
|
/* 2) march verifying 0000...0001 , writing 0000...0010 */
|
|
/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
|
|
/* the write mask equals 1000...0000 */
|
|
/* 4) march verifying 1000...0000 */
|
|
/* The test fails if any of the memory marches return a failure. */
|
|
/* */
|
|
/* OUTPUTS: */
|
|
/* Displays which pass on the memory test is executing */
|
|
/* */
|
|
/* RETURNS: */
|
|
/* 0 - Passed test */
|
|
/* 1 - Failed test */
|
|
/* */
|
|
/* RESTRICTIONS/LIMITATIONS: */
|
|
/* */
|
|
/* */
|
|
/*********************************************************************/
|
|
int mem_test_walk (void)
|
|
{
|
|
unsigned long long mask;
|
|
volatile unsigned long long *pmem =
|
|
(volatile unsigned long long *) CFG_MEMTEST_START;
|
|
const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
|
|
|
|
unsigned int i;
|
|
|
|
mask = 0x01;
|
|
|
|
printf ("Initial Pass");
|
|
mem_march (pmem, size, 0x0, 0x1, 0, 1);
|
|
|
|
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
|
|
printf (" ");
|
|
printf (" ");
|
|
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
|
|
|
|
for (i = 0; i < 63; i++) {
|
|
printf ("Pass %2d", i + 2);
|
|
if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
|
|
/*printf("mask: 0x%x, pass: %d, ", mask, i); */
|
|
return 1;
|
|
}
|
|
mask = mask << 1;
|
|
printf ("\b\b\b\b\b\b\b");
|
|
}
|
|
|
|
printf ("Last Pass");
|
|
if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
|
|
/* printf("mask: 0x%x", mask); */
|
|
return 1;
|
|
}
|
|
printf ("\b\b\b\b\b\b\b\b\b");
|
|
printf (" ");
|
|
printf ("\b\b\b\b\b\b\b\b\b");
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*********************************************************************/
|
|
/* NAME: testdram() - calls any enabled memory tests */
|
|
/* */
|
|
/* DESCRIPTION: */
|
|
/* Runs memory tests if the environment test variables are set to */
|
|
/* 'y'. */
|
|
/* */
|
|
/* INPUTS: */
|
|
/* testdramdata - If set to 'y', data test is run. */
|
|
/* testdramaddress - If set to 'y', address test is run. */
|
|
/* testdramwalk - If set to 'y', walking ones test is run */
|
|
/* */
|
|
/* OUTPUTS: */
|
|
/* None */
|
|
/* */
|
|
/* RETURNS: */
|
|
/* 0 - Passed test */
|
|
/* 1 - Failed test */
|
|
/* */
|
|
/* RESTRICTIONS/LIMITATIONS: */
|
|
/* */
|
|
/* */
|
|
/*********************************************************************/
|
|
int testdram (void)
|
|
{
|
|
char *s;
|
|
int rundata = 0;
|
|
int runaddress = 0;
|
|
int runwalk = 0;
|
|
|
|
#ifdef CFG_DRAM_TEST_DATA
|
|
s = getenv ("testdramdata");
|
|
rundata = (s && (*s == 'y')) ? 1 : 0;
|
|
#endif
|
|
#ifdef CFG_DRAM_TEST_ADDRESS
|
|
s = getenv ("testdramaddress");
|
|
runaddress = (s && (*s == 'y')) ? 1 : 0;
|
|
#endif
|
|
#ifdef CFG_DRAM_TEST_WALK
|
|
s = getenv ("testdramwalk");
|
|
runwalk = (s && (*s == 'y')) ? 1 : 0;
|
|
#endif
|
|
|
|
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
|
|
printf ("Testing RAM from 0x%08x to 0x%08x ... "
|
|
"(don't panic... that will take a moment !!!!)\n",
|
|
CFG_MEMTEST_START, CFG_MEMTEST_END);
|
|
#ifdef CFG_DRAM_TEST_DATA
|
|
if (rundata == 1) {
|
|
printf ("Test DATA ... ");
|
|
if (mem_test_data () == 1) {
|
|
printf ("failed \n");
|
|
return 1;
|
|
} else
|
|
printf ("ok \n");
|
|
}
|
|
#endif
|
|
#ifdef CFG_DRAM_TEST_ADDRESS
|
|
if (runaddress == 1) {
|
|
printf ("Test ADDRESS ... ");
|
|
if (mem_test_address () == 1) {
|
|
printf ("failed \n");
|
|
return 1;
|
|
} else
|
|
printf ("ok \n");
|
|
}
|
|
#endif
|
|
#ifdef CFG_DRAM_TEST_WALK
|
|
if (runwalk == 1) {
|
|
printf ("Test WALKING ONEs ... ");
|
|
if (mem_test_walk () == 1) {
|
|
printf ("failed \n");
|
|
return 1;
|
|
} else
|
|
printf ("ok \n");
|
|
}
|
|
#endif
|
|
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
|
|
printf ("passed\n");
|
|
return 0;
|
|
|
|
}
|
|
#endif /* CFG_DRAM_TEST */
|
|
|
|
/* ronen - the below functions are used by the bootm function */
|
|
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
|
|
/* - we turn off the RX gig dmas - to prevent the dma from overunning */
|
|
/* the kernel data areas. */
|
|
/* - we diable and invalidate the icache and dcache. */
|
|
void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
|
|
{
|
|
u32 temp;
|
|
|
|
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
|
|
if ((temp & 0xffff) == new_loc >> 16)
|
|
return;
|
|
|
|
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
|
|
0xffff0000) | (new_loc >> 16);
|
|
|
|
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
|
|
|
|
while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
|
|
new_loc |
|
|
(INTERNAL_SPACE_DECODE)))))
|
|
!= temp);
|
|
|
|
}
|
|
|