upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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54 lines
1.3 KiB
54 lines
1.3 KiB
/*
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* Copyright (C) 2013 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/system.h>
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#include <asm/arch/led.h>
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#include <asm/arch/sbc-regs.h>
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/* Entry point of U-Boot main program for the secondary CPU */
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LENTRY(secondary_entry)
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
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bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable
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mcr p15, 0, r0, c1, c0, 0
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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dsb
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led_write(C,0,,)
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ldr r1, =ROM_BOOT_ROMRSV2
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mov r0, #0
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str r0, [r1]
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0: wfe
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ldr r4, [r1] @ r4: entry point for secondary CPUs
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cmp r4, #0
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beq 0b
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led_write(C, P, U, 1)
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bx r4 @ secondary CPUs jump to linux
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ENDPROC(secondary_entry)
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ENTRY(wakeup_secondary)
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ldr r1, =ROM_BOOT_ROMRSV2
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0: ldr r0, [r1]
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cmp r0, #0
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bne 0b
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/* set entry address and send event to the secondary CPU */
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ldr r0, =secondary_entry
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str r0, [r1]
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ldr r0, [r1] @ make sure store is complete
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mov r0, #0x100
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0: subs r0, r0, #1 @ I don't know the reason, but without this wait
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bne 0b @ fails to wake up the secondary CPU
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sev
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/* wait until the secondary CPU reach to secondary_entry */
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0: ldr r0, [r1]
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cmp r0, #0
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bne 0b
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bx lr
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ENDPROC(wakeup_secondary)
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