upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Philipp Tomsich ba3bf3879e rockchip: clk: rk3399: 24MHz is not a power of 2 ... The clock driver for the RK3399 mistakenly used (24 * 2^20) where it should have used (24 * 10^6) in a few calculations. This commits fixes this. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>		7 years ago
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aspeed	aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation	7 years ago
at91	dm: allow limiting pre-reloc markings to spl or tpl	7 years ago
exynos	…
rockchip	rockchip: clk: rk3399: 24MHz is not a power of 2	7 years ago
tegra	…
uniphier	clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clock	7 years ago
Kconfig	clk: zynq: Add zynq clock framework driver	7 years ago
Makefile	clk: stm32f7: add clock driver for stm32f7 family	7 years ago
clk-uclass.c	dm: core: Replace of_offset with accessor	7 years ago
clk_boston.c	…
clk_fixed_rate.c	dm: core: Replace of_offset with accessor	7 years ago
clk_pic32.c	dm: core: Replace of_offset with accessor	7 years ago
clk_sandbox.c	…
clk_sandbox_test.c	…
clk_stm32f7.c	stm32f7: clk: remove usart1 clock enable from board init	7 years ago
clk_zynq.c	clk: zynq: Add optional ethernet emio clock source support	7 years ago
clk_zynqmp.c	clk: zynqmp: Add clock driver support for zynqmp	8 years ago