upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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459 lines
12 KiB
459 lines
12 KiB
/*
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* SoC-specific lowlevel code for tms320dm365 and similar chips
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* Actually used for booting from NAND with nand_spl.
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*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <nand.h>
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#include <ns16550.h>
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#include <post.h>
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#include <asm/arch/dm365_lowlevel.h>
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#include <asm/arch/hardware.h>
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void dm365_waitloop(unsigned long loopcnt)
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{
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unsigned long i;
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for (i = 0; i < loopcnt; i++)
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asm(" NOP");
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}
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int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
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{
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unsigned int clksrc = 0x0;
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/* Power up the PLL */
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clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
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clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
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setbits_le32(&dv_pll0_regs->pllctl,
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clksrc << PLLCTL_CLOCK_MODE_SHIFT);
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/*
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* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
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* through MMR
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*/
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clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
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/* Set PLLEN=0 => PLL BYPASS MODE */
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clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
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dm365_waitloop(150);
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/* PLLRST=1(reset assert) */
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setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
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dm365_waitloop(300);
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/*Bring PLL out of Reset*/
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clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
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/* Program the Multiper and Pre-Divider for PLL1 */
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writel(pllmult, &dv_pll0_regs->pllm);
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writel(prediv, &dv_pll0_regs->prediv);
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/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
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PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
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/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
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&dv_pll0_regs->secctl);
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/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
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writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
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/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
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/* Program the PostDiv for PLL1 */
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writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
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/* Post divider setting for PLL1 */
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
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writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
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dm365_waitloop(300);
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/* Set the GOSET bit */
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writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
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dm365_waitloop(300);
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/* Wait for PLL to LOCK */
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while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
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== PLL0_LOCK))
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;
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/* Enable the PLL Bit of PLLCTL*/
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setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
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return 0;
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}
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int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
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{
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unsigned int clksrc = 0x0;
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/* Power up the PLL*/
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clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
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/*
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* Select the Clock Mode as Onchip Oscilator or External Clock on
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* MXI pin
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* VDB has input on MXI pin
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*/
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clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
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setbits_le32(&dv_pll1_regs->pllctl,
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clksrc << PLLCTL_CLOCK_MODE_SHIFT);
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/*
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* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
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* through MMR
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*/
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clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
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/* Set PLLEN=0 => PLL BYPASS MODE */
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clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
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dm365_waitloop(50);
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/* PLLRST=1(reset assert) */
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setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
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dm365_waitloop(300);
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/* Bring PLL out of Reset */
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clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
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/* Program the Multiper and Pre-Divider for PLL2 */
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writel(pllm, &dv_pll1_regs->pllm);
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writel(prediv, &dv_pll1_regs->prediv);
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writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
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/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
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PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
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/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
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&dv_pll1_regs->secctl);
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/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
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writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
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/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
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writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
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/* Post divider setting for PLL2 */
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writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
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writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
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writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
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writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
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writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
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/* GoCmd for PostDivider to take effect */
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writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
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dm365_waitloop(150);
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/* Wait for PLL to LOCK */
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while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
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== PLL1_LOCK))
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;
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dm365_waitloop(4100);
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/* Enable the PLL2 */
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setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
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/* do this after PLL's have been set up */
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writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
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&dv_sys_module_regs->peri_clkctl);
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return 0;
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}
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int dm365_ddr_setup(void)
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{
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lpsc_on(DAVINCI_LPSC_DDR_EMIF);
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clrbits_le32(&dv_sys_module_regs->vtpiocr,
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VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
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/* Set bit CLRZ (bit 13) */
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setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
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/* Check VTP READY Status */
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while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
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;
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/* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
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setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
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/* Set bit LOCK(bit7) */
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setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
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/*
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* Powerdown VTP as it is locked (bit 6)
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* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
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*/
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setbits_le32(&dv_sys_module_regs->vtpiocr,
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VPTIO_IOPWRDN | VPTIO_PWRDN);
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/* Wait for calibration to complete */
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dm365_waitloop(150);
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/* Set the DDR2 to synreset, then enable it again */
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lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
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lpsc_on(DAVINCI_LPSC_DDR_EMIF);
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writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
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/* Program SDRAM Bank Config Register */
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writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
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&dv_ddr2_regs_ctrl->sdbcr);
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writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
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&dv_ddr2_regs_ctrl->sdbcr);
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/* Program SDRAM Timing Control Register1 */
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writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
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/* Program SDRAM Timing Control Register2 */
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writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
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writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
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writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
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/* Program SDRAM Refresh Control Register */
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writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
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lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
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lpsc_on(DAVINCI_LPSC_DDR_EMIF);
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return 0;
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}
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static void dm365_vpss_sync_reset(void)
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{
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unsigned int PdNum = 0;
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/* VPSS_CLKMD 1:1 */
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setbits_le32(&dv_sys_module_regs->vpss_clkctl,
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VPSS_CLK_CTL_VPSS_CLKMD);
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/* LPSC SyncReset DDR Clock Enable */
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writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
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~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
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&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
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writel((1 << PdNum), &dv_psc_regs->ptcmd);
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while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
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;
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while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
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PSC_MD_STATE_MSK) == PSC_SYNCRESET))
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;
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}
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static void dm365_por_reset(void)
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{
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struct davinci_timer *wdog =
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(struct davinci_timer *)DAVINCI_WDOG_BASE;
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if (readl(&dv_pll0_regs->rstype) &
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(PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
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dm365_vpss_sync_reset();
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writel(DV_TMPBUF_VAL, TMPBUF);
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setbits_le32(TMPSTATUS, FLAG_PORRST);
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writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
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writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
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while (1);
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}
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}
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static void dm365_wdt_reset(void)
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{
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struct davinci_timer *wdog =
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(struct davinci_timer *)DAVINCI_WDOG_BASE;
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if (readl(TMPBUF) != DV_TMPBUF_VAL) {
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writel(DV_TMPBUF_VAL, TMPBUF);
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setbits_le32(TMPSTATUS, FLAG_PORRST);
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setbits_le32(TMPSTATUS, FLAG_FLGOFF);
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dm365_waitloop(100);
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dm365_vpss_sync_reset();
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writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
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writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
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while (1);
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}
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}
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static void dm365_wdt_flag_on(void)
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{
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/* VPSS_CLKMD 1:2 */
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clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
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VPSS_CLK_CTL_VPSS_CLKMD);
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writel(0, TMPBUF);
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setbits_le32(TMPSTATUS, FLAG_FLGON);
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}
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void dm365_psc_init(void)
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{
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unsigned char i = 0;
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unsigned char lpsc_start;
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unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
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unsigned int PdNum = 0;
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lpscmin = 0;
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lpscmax = 2;
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for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
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if (lpscgroup == 0) {
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/* Enabling LPSC 3 to 28 SCR first */
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lpsc_start = DAVINCI_LPSC_VPSSMSTR;
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lpsc_end = DAVINCI_LPSC_TIMER1;
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} else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
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lpsc_start = DAVINCI_LPSC_CFG5;
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lpsc_end = DAVINCI_LPSC_VPSSMASTER;
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} else {
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lpsc_start = DAVINCI_LPSC_MJCP;
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lpsc_end = DAVINCI_LPSC_HDVICP;
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}
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/* NEXT=0x3, Enable LPSC's */
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for (i = lpsc_start; i <= lpsc_end; i++)
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setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
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/*
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* Program goctl to start transition sequence for LPSCs
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* CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
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* Domain 0 Modules
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*/
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writel((1 << PdNum), &dv_psc_regs->ptcmd);
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/*
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* Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
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*/
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while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
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== 0))
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;
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/* Wait for MODSTAT = ENABLE from LPSC's */
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for (i = lpsc_start; i <= lpsc_end; i++)
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while (!((readl(&dv_psc_regs->mdstat[i]) &
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PSC_MD_STATE_MSK) == PSC_ENABLE))
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;
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}
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}
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static void dm365_emif_init(void)
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{
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writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
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writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
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setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
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writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
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return;
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}
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void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
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unsigned long value)
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{
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clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
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setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
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}
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__attribute__((weak))
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void board_gpio_init(void)
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{
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return;
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}
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#if defined(CONFIG_POST)
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int post_log(char *format, ...)
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{
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return 0;
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}
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#endif
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void dm36x_lowlevel_init(ulong bootflag)
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{
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struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
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(struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
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DAVINCI_UART_CTRL_BASE);
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/* Mask all interrupts */
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writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
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writel(0x0, &dv_aintc_regs->eabase);
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writel(0x0, &dv_aintc_regs->eint0);
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writel(0x0, &dv_aintc_regs->eint1);
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/* Clear all interrupts */
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writel(0xffffffff, &dv_aintc_regs->fiq0);
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writel(0xffffffff, &dv_aintc_regs->fiq1);
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writel(0xffffffff, &dv_aintc_regs->irq0);
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writel(0xffffffff, &dv_aintc_regs->irq1);
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dm365_por_reset();
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dm365_wdt_reset();
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/* System PSC setup - enable all */
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dm365_psc_init();
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/* Setup Pinmux */
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dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
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dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
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dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
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dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
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dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
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/* PLL setup */
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dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
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CONFIG_SYS_DM36x_PLL1_PREDIV);
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dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
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CONFIG_SYS_DM36x_PLL2_PREDIV);
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/* GPIO setup */
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board_gpio_init();
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NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
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CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
|
|
|
|
/*
|
|
* Fix Power and Emulation Management Register
|
|
* see sprufh2.pdf page 38 Table 22
|
|
*/
|
|
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
|
|
DAVINCI_UART_PWREMU_MGMT_UTRST),
|
|
&davinci_uart_ctrl_regs->pwremu_mgmt);
|
|
|
|
puts("ddr init\n");
|
|
dm365_ddr_setup();
|
|
|
|
puts("emif init\n");
|
|
dm365_emif_init();
|
|
|
|
dm365_wdt_flag_on();
|
|
|
|
#if defined(CONFIG_POST)
|
|
/*
|
|
* Do memory tests, calls arch_memory_failure_handle()
|
|
* if error detected.
|
|
*/
|
|
memory_post_test(0);
|
|
#endif
|
|
}
|
|
|