upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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156 lines
3.9 KiB
156 lines
3.9 KiB
/*
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* (C) Copyright 2006-2010
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* Texas Instruments, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CPU_H
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#define _CPU_H
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct gpmc_cs {
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u32 config1; /* 0x00 */
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u32 config2; /* 0x04 */
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u32 config3; /* 0x08 */
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u32 config4; /* 0x0C */
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u32 config5; /* 0x10 */
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u32 config6; /* 0x14 */
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u32 config7; /* 0x18 */
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u32 nand_cmd; /* 0x1C */
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u32 nand_adr; /* 0x20 */
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u32 nand_dat; /* 0x24 */
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u8 res[8]; /* blow up to 0x30 byte */
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};
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struct gpmc {
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u8 res1[0x10];
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u32 sysconfig; /* 0x10 */
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u8 res2[0x4];
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u32 irqstatus; /* 0x18 */
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u32 irqenable; /* 0x1C */
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u8 res3[0x20];
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u32 timeout_control; /* 0x40 */
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u8 res4[0xC];
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u32 config; /* 0x50 */
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u32 status; /* 0x54 */
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u8 res5[0x8]; /* 0x58 */
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struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
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u8 res6[0x14]; /* 0x1E0 */
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u32 ecc_config; /* 0x1F4 */
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u32 ecc_control; /* 0x1F8 */
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u32 ecc_size_config; /* 0x1FC */
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u32 ecc1_result; /* 0x200 */
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u32 ecc2_result; /* 0x204 */
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u32 ecc3_result; /* 0x208 */
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u32 ecc4_result; /* 0x20C */
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u32 ecc5_result; /* 0x210 */
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u32 ecc6_result; /* 0x214 */
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u32 ecc7_result; /* 0x218 */
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u32 ecc8_result; /* 0x21C */
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u32 ecc9_result; /* 0x220 */
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};
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/* Used for board specific gpmc initialization */
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extern struct gpmc *gpmc_cfg;
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struct gptimer {
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u32 tidr; /* 0x00 r */
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u8 res[0xc];
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u32 tiocp_cfg; /* 0x10 rw */
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u32 tistat; /* 0x14 r */
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u32 tisr; /* 0x18 rw */
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u32 tier; /* 0x1c rw */
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u32 twer; /* 0x20 rw */
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u32 tclr; /* 0x24 rw */
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u32 tcrr; /* 0x28 rw */
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u32 tldr; /* 0x2c rw */
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u32 ttgr; /* 0x30 rw */
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u32 twpc; /* 0x34 r */
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u32 tmar; /* 0x38 rw */
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u32 tcar1; /* 0x3c r */
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u32 tcicr; /* 0x40 rw */
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u32 tcar2; /* 0x44 r */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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/* enable sys_clk NO-prescale /1 */
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#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
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/* Watchdog */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct watchdog {
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u8 res1[0x34];
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u32 wwps; /* 0x34 r */
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u8 res2[0x10];
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u32 wspr; /* 0x48 rw */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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#define TCLR_ST (0x1 << 0)
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#define TCLR_AR (0x1 << 1)
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#define TCLR_PRE (0x1 << 5)
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/* GPMC BASE */
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#define GPMC_BASE (OMAP44XX_GPMC_BASE)
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/* I2C base */
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#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000)
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#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
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#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000)
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#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000)
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/* MUSB base */
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#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000)
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/* OMAP4 GPIO registers */
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#define OMAP_GPIO_REVISION 0x0000
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#define OMAP_GPIO_SYSCONFIG 0x0010
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#define OMAP_GPIO_SYSSTATUS 0x0114
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#define OMAP_GPIO_IRQSTATUS1 0x0118
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#define OMAP_GPIO_IRQSTATUS2 0x0128
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#define OMAP_GPIO_IRQENABLE2 0x012c
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#define OMAP_GPIO_IRQENABLE1 0x011c
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#define OMAP_GPIO_WAKE_EN 0x0120
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#define OMAP_GPIO_CTRL 0x0130
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#define OMAP_GPIO_OE 0x0134
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#define OMAP_GPIO_DATAIN 0x0138
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#define OMAP_GPIO_DATAOUT 0x013c
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#define OMAP_GPIO_LEVELDETECT0 0x0140
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#define OMAP_GPIO_LEVELDETECT1 0x0144
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#define OMAP_GPIO_RISINGDETECT 0x0148
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#define OMAP_GPIO_FALLINGDETECT 0x014c
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#define OMAP_GPIO_DEBOUNCE_EN 0x0150
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#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
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#define OMAP_GPIO_CLEARIRQENABLE1 0x0160
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#define OMAP_GPIO_SETIRQENABLE1 0x0164
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#define OMAP_GPIO_CLEARWKUENA 0x0180
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#define OMAP_GPIO_SETWKUENA 0x0184
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#define OMAP_GPIO_CLEARDATAOUT 0x0190
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#define OMAP_GPIO_SETDATAOUT 0x0194
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/*
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* PRCM
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*/
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/* PRM */
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#define PRM_BASE 0x4A306000
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#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
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#define PRM_RSTCTRL PRM_DEVICE_BASE
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#define PRM_RSTCTRL_RESET 0x01
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#define PRM_RSTST (PRM_DEVICE_BASE + 0x4)
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#define PRM_RSTST_WARM_RESET_MASK 0x07EA
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#endif /* _CPU_H */
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