upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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155 lines
3.2 KiB
155 lines
3.2 KiB
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* Copyright (c) 2013 NVIDIA Corporation
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _TEGRA20_USB_H_
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#define _TEGRA20_USB_H_
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/* USB Controller (USBx_CONTROLLER_) regs */
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struct usb_ctlr {
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/* 0x000 */
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uint id;
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uint reserved0;
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uint host;
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uint device;
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/* 0x010 */
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uint txbuf;
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uint rxbuf;
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uint reserved1[2];
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/* 0x020 */
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uint reserved2[56];
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/* 0x100 */
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u16 cap_length;
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u16 hci_version;
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uint hcs_params;
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uint hcc_params;
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uint reserved3[5];
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/* 0x120 */
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uint dci_version;
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uint dcc_params;
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uint reserved4[6];
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/* 0x140 */
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uint usb_cmd;
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uint usb_sts;
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uint usb_intr;
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uint frindex;
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/* 0x150 */
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uint reserved5;
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uint periodic_list_base;
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uint async_list_addr;
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uint async_tt_sts;
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/* 0x160 */
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uint burst_size;
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uint tx_fill_tuning;
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uint reserved6; /* is this port_sc1 on some controllers? */
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uint icusb_ctrl;
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/* 0x170 */
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uint ulpi_viewport;
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uint reserved7;
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uint endpt_nak;
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uint endpt_nak_enable;
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/* 0x180 */
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uint reserved;
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uint port_sc1;
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uint reserved8[6];
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/* 0x1a0 */
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uint reserved9;
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uint otgsc;
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uint usb_mode;
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uint endpt_setup_stat;
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/* 0x1b0 */
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uint reserved10[20];
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/* 0x200 */
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uint reserved11[0x80];
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/* 0x400 */
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uint susp_ctrl;
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uint phy_vbus_sensors;
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uint phy_vbus_wakeup_id;
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uint phy_alt_vbus_sys;
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/* 0x410 */
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uint usb1_legacy_ctrl;
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uint reserved12[4];
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/* 0x424 */
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uint ulpi_timing_ctrl_0;
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uint ulpi_timing_ctrl_1;
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uint reserved13[53];
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/* 0x500 */
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uint reserved14[64 * 3];
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/* 0x800 */
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uint utmip_pll_cfg0;
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uint utmip_pll_cfg1;
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uint utmip_xcvr_cfg0;
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uint utmip_bias_cfg0;
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/* 0x810 */
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uint utmip_hsrx_cfg0;
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uint utmip_hsrx_cfg1;
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uint utmip_fslsrx_cfg0;
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uint utmip_fslsrx_cfg1;
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/* 0x820 */
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uint utmip_tx_cfg0;
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uint utmip_misc_cfg0;
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uint utmip_misc_cfg1;
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uint utmip_debounce_cfg0;
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/* 0x830 */
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uint utmip_bat_chrg_cfg0;
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uint utmip_spare_cfg0;
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uint utmip_xcvr_cfg1;
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uint utmip_bias_cfg1;
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};
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/* USB2_IF_ULPI_TIMING_CTRL_0 */
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#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
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#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
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/* USB2_IF_ULPI_TIMING_CTRL_1 */
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#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
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#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
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#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
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#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
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#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
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#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
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/* PORTSC, USB2, USB3 */
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#define PTS_SHIFT 30
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#define PTS_MASK (3U << PTS_SHIFT)
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#define STS (1 << 29)
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#endif /* _TEGRA20_USB_H_ */
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