upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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417 lines
12 KiB
417 lines
12 KiB
/*
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* MPC823 and PXA LCD Controller
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*
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* Modeled after video interface by Paolo Scaffardi
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*
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*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _LCD_H_
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#define _LCD_H_
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extern char lcd_is_enabled;
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extern int lcd_line_length;
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extern struct vidinfo panel_info;
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void lcd_ctrl_init(void *lcdbase);
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void lcd_enable(void);
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/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
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void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue);
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void lcd_initcolregs(void);
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/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
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struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
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void **alloc_addr);
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int bmp_display(ulong addr, int x, int y);
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/**
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* Set whether we need to flush the dcache when changing the LCD image. This
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* defaults to off.
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*
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* @param flush non-zero to flush cache after update, 0 to skip
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*/
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void lcd_set_flush_dcache(int flush);
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#if defined CONFIG_MPC823
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/*
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* LCD controller stucture for MPC823 CPU
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*/
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typedef struct vidinfo {
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ushort vl_col; /* Number of columns (i.e. 640) */
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ushort vl_row; /* Number of rows (i.e. 480) */
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ushort vl_width; /* Width of display area in millimeters */
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ushort vl_height; /* Height of display area in millimeters */
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/* LCD configuration register */
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u_char vl_clkp; /* Clock polarity */
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u_char vl_oep; /* Output Enable polarity */
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u_char vl_hsp; /* Horizontal Sync polarity */
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u_char vl_vsp; /* Vertical Sync polarity */
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u_char vl_dp; /* Data polarity */
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u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
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u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
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u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
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u_char vl_clor; /* Color, 0 = mono, 1 = color */
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u_char vl_tft; /* 0 = passive, 1 = TFT */
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/* Horizontal control register. Timing from data sheet */
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ushort vl_wbl; /* Wait between lines */
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/* Vertical control register */
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u_char vl_vpw; /* Vertical sync pulse width */
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u_char vl_lcdac; /* LCD AC timing */
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u_char vl_wbf; /* Wait between frames */
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} vidinfo_t;
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#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
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defined CONFIG_CPU_MONAHANS
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/*
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* PXA LCD DMA descriptor
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*/
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struct pxafb_dma_descriptor {
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u_long fdadr; /* Frame descriptor address register */
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u_long fsadr; /* Frame source address register */
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u_long fidr; /* Frame ID register */
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u_long ldcmd; /* Command register */
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};
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/*
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* PXA LCD info
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*/
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struct pxafb_info {
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/* Misc registers */
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u_long reg_lccr3;
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u_long reg_lccr2;
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u_long reg_lccr1;
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u_long reg_lccr0;
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u_long fdadr0;
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u_long fdadr1;
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/* DMA descriptors */
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struct pxafb_dma_descriptor * dmadesc_fblow;
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struct pxafb_dma_descriptor * dmadesc_fbhigh;
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struct pxafb_dma_descriptor * dmadesc_palette;
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u_long screen; /* physical address of frame buffer */
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u_long palette; /* physical address of palette memory */
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u_int palette_size;
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};
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/*
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* LCD controller stucture for PXA CPU
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*/
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typedef struct vidinfo {
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ushort vl_col; /* Number of columns (i.e. 640) */
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ushort vl_row; /* Number of rows (i.e. 480) */
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ushort vl_width; /* Width of display area in millimeters */
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ushort vl_height; /* Height of display area in millimeters */
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/* LCD configuration register */
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u_char vl_clkp; /* Clock polarity */
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u_char vl_oep; /* Output Enable polarity */
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u_char vl_hsp; /* Horizontal Sync polarity */
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u_char vl_vsp; /* Vertical Sync polarity */
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u_char vl_dp; /* Data polarity */
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u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
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u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
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u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
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u_char vl_clor; /* Color, 0 = mono, 1 = color */
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u_char vl_tft; /* 0 = passive, 1 = TFT */
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/* Horizontal control register. Timing from data sheet */
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ushort vl_hpw; /* Horz sync pulse width */
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u_char vl_blw; /* Wait before of line */
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u_char vl_elw; /* Wait end of line */
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/* Vertical control register. */
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u_char vl_vpw; /* Vertical sync pulse width */
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u_char vl_bfw; /* Wait before of frame */
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u_char vl_efw; /* Wait end of frame */
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/* PXA LCD controller params */
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struct pxafb_info pxa;
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} vidinfo_t;
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#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
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typedef struct vidinfo {
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ushort vl_col; /* Number of columns (i.e. 640) */
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ushort vl_row; /* Number of rows (i.e. 480) */
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u_long vl_clk; /* pixel clock in ps */
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/* LCD configuration register */
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u_long vl_sync; /* Horizontal / vertical sync */
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u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
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u_long vl_tft; /* 0 = passive, 1 = TFT */
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u_long vl_cont_pol_low; /* contrast polarity is low */
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u_long vl_clk_pol; /* clock polarity */
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/* Horizontal control register. */
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u_long vl_hsync_len; /* Length of horizontal sync */
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u_long vl_left_margin; /* Time from sync to picture */
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u_long vl_right_margin; /* Time from picture to sync */
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/* Vertical control register. */
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u_long vl_vsync_len; /* Length of vertical sync */
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u_long vl_upper_margin; /* Time from sync to picture */
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u_long vl_lower_margin; /* Time from picture to sync */
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u_long mmio; /* Memory mapped registers */
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} vidinfo_t;
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#elif defined(CONFIG_EXYNOS_FB)
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enum {
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FIMD_RGB_INTERFACE = 1,
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FIMD_CPU_INTERFACE = 2,
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};
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enum exynos_fb_rgb_mode_t {
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MODE_RGB_P = 0,
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MODE_BGR_P = 1,
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MODE_RGB_S = 2,
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MODE_BGR_S = 3,
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};
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typedef struct vidinfo {
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ushort vl_col; /* Number of columns (i.e. 640) */
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ushort vl_row; /* Number of rows (i.e. 480) */
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ushort vl_width; /* Width of display area in millimeters */
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ushort vl_height; /* Height of display area in millimeters */
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/* LCD configuration register */
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u_char vl_freq; /* Frequency */
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u_char vl_clkp; /* Clock polarity */
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u_char vl_oep; /* Output Enable polarity */
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u_char vl_hsp; /* Horizontal Sync polarity */
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u_char vl_vsp; /* Vertical Sync polarity */
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u_char vl_dp; /* Data polarity */
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u_char vl_bpix; /* Bits per pixel */
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/* Horizontal control register. Timing from data sheet */
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u_char vl_hspw; /* Horz sync pulse width */
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u_char vl_hfpd; /* Wait before of line */
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u_char vl_hbpd; /* Wait end of line */
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/* Vertical control register. */
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u_char vl_vspw; /* Vertical sync pulse width */
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u_char vl_vfpd; /* Wait before of frame */
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u_char vl_vbpd; /* Wait end of frame */
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u_char vl_cmd_allow_len; /* Wait end of frame */
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unsigned int win_id;
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unsigned int init_delay;
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unsigned int power_on_delay;
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unsigned int reset_delay;
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unsigned int interface_mode;
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unsigned int mipi_enabled;
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unsigned int dp_enabled;
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unsigned int cs_setup;
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unsigned int wr_setup;
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unsigned int wr_act;
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unsigned int wr_hold;
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unsigned int logo_on;
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unsigned int logo_width;
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unsigned int logo_height;
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int logo_x_offset;
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int logo_y_offset;
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unsigned long logo_addr;
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unsigned int rgb_mode;
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unsigned int resolution;
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/* parent clock name(MPLL, EPLL or VPLL) */
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unsigned int pclk_name;
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/* ratio value for source clock from parent clock. */
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unsigned int sclk_div;
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unsigned int dual_lcd_enabled;
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} vidinfo_t;
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void init_panel_info(vidinfo_t *vid);
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#else
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typedef struct vidinfo {
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ushort vl_col; /* Number of columns (i.e. 160) */
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ushort vl_row; /* Number of rows (i.e. 100) */
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u_char vl_bpix; /* Bits per pixel, 0 = 1 */
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ushort *cmap; /* Pointer to the colormap */
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void *priv; /* Pointer to driver-specific data */
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} vidinfo_t;
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#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
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extern vidinfo_t panel_info;
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/* Video functions */
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void lcd_putc(const char c);
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void lcd_puts(const char *s);
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void lcd_printf(const char *fmt, ...);
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void lcd_clear(void);
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int lcd_display_bitmap(ulong bmp_image, int x, int y);
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/**
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* Get the width of the LCD in pixels
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*
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* @return width of LCD in pixels
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*/
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int lcd_get_pixel_width(void);
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/**
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* Get the height of the LCD in pixels
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*
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* @return height of LCD in pixels
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*/
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int lcd_get_pixel_height(void);
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/**
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* Get the number of text lines/rows on the LCD
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*
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* @return number of rows
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*/
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int lcd_get_screen_rows(void);
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/**
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* Get the number of text columns on the LCD
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*
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* @return number of columns
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*/
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int lcd_get_screen_columns(void);
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/**
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* Set the position of the text cursor
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*
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* @param col Column to place cursor (0 = left side)
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* @param row Row to place cursor (0 = top line)
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*/
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void lcd_position_cursor(unsigned col, unsigned row);
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/* Allow boards to customize the information displayed */
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void lcd_show_board_info(void);
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/* Return the size of the LCD frame buffer, and the line length */
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int lcd_get_size(int *line_length);
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int lcd_dt_simplefb_add_node(void *blob);
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int lcd_dt_simplefb_enable_existing_node(void *blob);
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/* Update the LCD / flush the cache */
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void lcd_sync(void);
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/************************************************************************/
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/* ** BITMAP DISPLAY SUPPORT */
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/************************************************************************/
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#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
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# include <bmp_layout.h>
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# include <asm/byteorder.h>
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#endif
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/*
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* Information about displays we are using. This is for configuring
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* the LCD controller and memory allocation. Someone has to know what
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* is connected, as we can't autodetect anything.
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*/
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#define CONFIG_SYS_HIGH 0 /* Pins are active high */
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#define CONFIG_SYS_LOW 1 /* Pins are active low */
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#define LCD_MONOCHROME 0
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#define LCD_COLOR2 1
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#define LCD_COLOR4 2
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#define LCD_COLOR8 3
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#define LCD_COLOR16 4
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#define LCD_COLOR32 5
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/*----------------------------------------------------------------------*/
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#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
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# define LCD_INFO_X 0
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# define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT)
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#elif defined(CONFIG_LCD_LOGO)
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# define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH)
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# define LCD_INFO_Y VIDEO_FONT_HEIGHT
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#else
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# define LCD_INFO_X VIDEO_FONT_WIDTH
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# define LCD_INFO_Y VIDEO_FONT_HEIGHT
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#endif
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/* Default to 8bpp if bit depth not specified */
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#ifndef LCD_BPP
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# define LCD_BPP LCD_COLOR8
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#endif
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#ifndef LCD_DF
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# define LCD_DF 1
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#endif
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/* Calculate nr. of bits per pixel and nr. of colors */
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#define NBITS(bit_code) (1 << (bit_code))
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#define NCOLORS(bit_code) (1 << NBITS(bit_code))
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/************************************************************************/
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/* ** CONSOLE CONSTANTS */
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/************************************************************************/
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#if LCD_BPP == LCD_MONOCHROME
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/*
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* Simple black/white definitions
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*/
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# define CONSOLE_COLOR_BLACK 0
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# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */
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#elif LCD_BPP == LCD_COLOR8
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/*
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* 8bpp color definitions
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*/
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# define CONSOLE_COLOR_BLACK 0
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# define CONSOLE_COLOR_RED 1
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# define CONSOLE_COLOR_GREEN 2
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# define CONSOLE_COLOR_YELLOW 3
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# define CONSOLE_COLOR_BLUE 4
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# define CONSOLE_COLOR_MAGENTA 5
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# define CONSOLE_COLOR_CYAN 6
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# define CONSOLE_COLOR_GREY 14
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# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
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#elif LCD_BPP == LCD_COLOR32
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/*
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* 32bpp color definitions
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*/
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# define CONSOLE_COLOR_RED 0x00ff0000
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# define CONSOLE_COLOR_GREEN 0x0000ff00
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# define CONSOLE_COLOR_YELLOW 0x00ffff00
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# define CONSOLE_COLOR_BLUE 0x000000ff
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# define CONSOLE_COLOR_MAGENTA 0x00ff00ff
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# define CONSOLE_COLOR_CYAN 0x0000ffff
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# define CONSOLE_COLOR_GREY 0x00aaaaaa
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# define CONSOLE_COLOR_BLACK 0x00000000
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# define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest*/
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# define NBYTES(bit_code) (NBITS(bit_code) >> 3)
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#else
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/*
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* 16bpp color definitions
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*/
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# define CONSOLE_COLOR_BLACK 0x0000
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# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
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#endif /* color definitions */
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/************************************************************************/
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#ifndef PAGE_SIZE
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# define PAGE_SIZE 4096
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#endif
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/************************************************************************/
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#endif /* _LCD_H_ */
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