upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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289 lines
7.0 KiB
289 lines
7.0 KiB
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _PCMCIA_H
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#define _PCMCIA_H
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#include <common.h>
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#include <config.h>
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/*
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* Allow configuration to select PCMCIA slot,
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* or try to generate a useful default
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*/
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#if defined(CONFIG_CMD_PCMCIA) || \
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(defined(CONFIG_CMD_IDE) && \
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(defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
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#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
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#if defined(CONFIG_TQM8xxL)
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# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
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#elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */
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# define CONFIG_PCMCIA_SLOT_B
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#elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
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# define CONFIG_PCMCIA_SLOT_A
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#elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */
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# define CONFIG_PCMCIA_SLOT_B
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#elif defined(CONFIG_ICU862) /* The ICU862 use SLOT_B */
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# define CONFIG_PCMCIA_SLOT_B
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#elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */
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# define CONFIG_PCMCIA_SLOT_B
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#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
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# define CONFIG_PCMCIA_SLOT_A
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#elif defined(CONFIG_UC100) /* The UC100 use SLOT_B */
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# define CONFIG_PCMCIA_SLOT_B
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#else
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# error "PCMCIA Slot not configured"
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#endif
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#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
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/* Make sure exactly one slot is defined - we support only one for now */
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#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
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#error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
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#endif
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#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
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#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
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#endif
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#ifndef PCMCIA_SOCKETS_NO
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#define PCMCIA_SOCKETS_NO 1
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#endif
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#ifndef PCMCIA_MEM_WIN_NO
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#define PCMCIA_MEM_WIN_NO 4
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#endif
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#define PCMCIA_IO_WIN_NO 2
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/* define _slot_ to be able to optimize macros */
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#ifdef CONFIG_PCMCIA_SLOT_A
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# define _slot_ 0
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# define PCMCIA_SLOT_MSG "slot A"
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# define PCMCIA_SLOT_x PCMCIA_PSLOT_A
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#else
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# define _slot_ 1
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# define PCMCIA_SLOT_MSG "slot B"
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# define PCMCIA_SLOT_x PCMCIA_PSLOT_B
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#endif
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/*
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* The TQM850L hardware has two pins swapped! Grrrrgh!
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*/
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#ifdef CONFIG_TQM850L
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#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
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#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
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#else
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#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
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#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
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#endif
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/*
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* This structure is used to address each window in the PCMCIA controller.
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*
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* Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
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* after pcmcia_win_t[n]...
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*/
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typedef struct {
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ulong br;
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ulong or;
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} pcmcia_win_t;
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/*
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* Definitions for PCMCIA control registers to operate in IDE mode
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*
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* All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
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* to be done later (depending on CPU clock)
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*/
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/* Window 0:
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* Base: 0xFE100000 CS1
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* Port Size: 2 Bytes
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* Port Size: 16 Bit
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* Common Memory Space
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*/
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#define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
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#define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
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| PCMCIA_PPS_16 \
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| PCMCIA_PRS_MEM \
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| PCMCIA_SLOT_x \
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| PCMCIA_PV \
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)
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/* Window 1:
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* Base: 0xFE100080 CS1
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* Port Size: 8 Bytes
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* Port Size: 8 Bit
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* Common Memory Space
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*/
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#define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
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#define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
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| PCMCIA_PPS_8 \
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| PCMCIA_PRS_MEM \
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| PCMCIA_SLOT_x \
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| PCMCIA_PV \
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)
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/* Window 2:
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* Base: 0xFE100100 CS2
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* Port Size: 8 Bytes
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* Port Size: 8 Bit
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* Common Memory Space
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*/
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#define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
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#define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
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| PCMCIA_PPS_8 \
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| PCMCIA_PRS_MEM \
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| PCMCIA_SLOT_x \
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| PCMCIA_PV \
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)
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/* Window 3:
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* not used
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*/
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#define CONFIG_SYS_PCMCIA_PBR3 0
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#define CONFIG_SYS_PCMCIA_POR3 0
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/* Window 4:
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* Base: 0xFE100C00 CS1
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* Port Size: 2 Bytes
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* Port Size: 16 Bit
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* Common Memory Space
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*/
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#define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
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#define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
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| PCMCIA_PPS_16 \
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| PCMCIA_PRS_MEM \
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| PCMCIA_SLOT_x \
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| PCMCIA_PV \
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)
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/* Window 5:
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* Base: 0xFE100C80 CS1
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* Port Size: 8 Bytes
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* Port Size: 8 Bit
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* Common Memory Space
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*/
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#define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
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#define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
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| PCMCIA_PPS_8 \
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| PCMCIA_PRS_MEM \
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| PCMCIA_SLOT_x \
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| PCMCIA_PV \
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)
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/* Window 6:
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* Base: 0xFE100D00 CS2
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* Port Size: 8 Bytes
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* Port Size: 8 Bit
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* Common Memory Space
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*/
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#define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
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#define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
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| PCMCIA_PPS_8 \
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| PCMCIA_PRS_MEM \
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| PCMCIA_SLOT_x \
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| PCMCIA_PV \
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)
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/* Window 7:
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* not used
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*/
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#define CONFIG_SYS_PCMCIA_PBR7 0
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#define CONFIG_SYS_PCMCIA_POR7 0
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/**********************************************************************/
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/*
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* CIS Tupel codes
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*/
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#define CISTPL_NULL 0x00
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#define CISTPL_DEVICE 0x01
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#define CISTPL_LONGLINK_CB 0x02
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#define CISTPL_INDIRECT 0x03
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#define CISTPL_CONFIG_CB 0x04
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#define CISTPL_CFTABLE_ENTRY_CB 0x05
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#define CISTPL_LONGLINK_MFC 0x06
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#define CISTPL_BAR 0x07
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#define CISTPL_PWR_MGMNT 0x08
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#define CISTPL_EXTDEVICE 0x09
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#define CISTPL_CHECKSUM 0x10
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#define CISTPL_LONGLINK_A 0x11
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#define CISTPL_LONGLINK_C 0x12
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#define CISTPL_LINKTARGET 0x13
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#define CISTPL_NO_LINK 0x14
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#define CISTPL_VERS_1 0x15
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#define CISTPL_ALTSTR 0x16
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#define CISTPL_DEVICE_A 0x17
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#define CISTPL_JEDEC_C 0x18
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#define CISTPL_JEDEC_A 0x19
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#define CISTPL_CONFIG 0x1a
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#define CISTPL_CFTABLE_ENTRY 0x1b
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#define CISTPL_DEVICE_OC 0x1c
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#define CISTPL_DEVICE_OA 0x1d
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#define CISTPL_DEVICE_GEO 0x1e
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#define CISTPL_DEVICE_GEO_A 0x1f
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#define CISTPL_MANFID 0x20
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#define CISTPL_FUNCID 0x21
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#define CISTPL_FUNCE 0x22
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#define CISTPL_SWIL 0x23
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#define CISTPL_END 0xff
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/*
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* CIS Function ID codes
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*/
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#define CISTPL_FUNCID_MULTI 0x00
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#define CISTPL_FUNCID_MEMORY 0x01
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#define CISTPL_FUNCID_SERIAL 0x02
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#define CISTPL_FUNCID_PARALLEL 0x03
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#define CISTPL_FUNCID_FIXED 0x04
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#define CISTPL_FUNCID_VIDEO 0x05
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#define CISTPL_FUNCID_NETWORK 0x06
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#define CISTPL_FUNCID_AIMS 0x07
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#define CISTPL_FUNCID_SCSI 0x08
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/*
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* Fixed Disk FUNCE codes
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*/
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#define CISTPL_IDE_INTERFACE 0x01
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#define CISTPL_FUNCE_IDE_IFACE 0x01
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#define CISTPL_FUNCE_IDE_MASTER 0x02
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#define CISTPL_FUNCE_IDE_SLAVE 0x03
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/* First feature byte */
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#define CISTPL_IDE_SILICON 0x04
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#define CISTPL_IDE_UNIQUE 0x08
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#define CISTPL_IDE_DUAL 0x10
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/* Second feature byte */
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#define CISTPL_IDE_HAS_SLEEP 0x01
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#define CISTPL_IDE_HAS_STANDBY 0x02
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#define CISTPL_IDE_HAS_IDLE 0x04
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#define CISTPL_IDE_LOW_POWER 0x08
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#define CISTPL_IDE_REG_INHIBIT 0x10
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#define CISTPL_IDE_HAS_INDEX 0x20
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#define CISTPL_IDE_IOIS16 0x40
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#endif
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#ifdef CONFIG_8xx
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extern u_int *pcmcia_pgcrx[];
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#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
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#endif
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#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
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extern int check_ide_device(int slot);
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#endif
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#endif /* _PCMCIA_H */
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