upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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167 lines
4.8 KiB
167 lines
4.8 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* Author: InKi Dae <inki.dae@samsung.com>
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* Author: Donghwa Lee <dh09.lee@samsung.com>
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*/
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#ifndef __ASM_ARM_ARCH_DSIM_H_
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#define __ASM_ARM_ARCH_DSIM_H_
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#ifndef __ASSEMBLY__
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struct exynos_mipi_dsim {
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unsigned int status;
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unsigned int swrst;
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unsigned int clkctrl;
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unsigned int timeout;
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unsigned int config;
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unsigned int escmode;
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unsigned int mdresol;
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unsigned int mvporch;
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unsigned int mhporch;
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unsigned int msync;
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unsigned int sdresol;
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unsigned int intsrc;
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unsigned int intmsk;
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unsigned int pkthdr;
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unsigned int payload;
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unsigned int rxfifo;
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unsigned int fifothld;
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unsigned int fifoctrl;
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unsigned int memacchr;
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unsigned int pllctrl;
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unsigned int plltmr;
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unsigned int phyacchr;
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unsigned int phyacchr1;
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};
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#endif /* __ASSEMBLY__ */
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/*
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* Bit Definitions
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*/
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/* DSIM_STATUS */
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#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
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#define DSIM_STOP_STATE_CLK (1 << 8)
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#define DSIM_TX_READY_HS_CLK (1 << 10)
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#define DSIM_PLL_STABLE (1 << 31)
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/* DSIM_SWRST */
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#define DSIM_FUNCRST (1 << 16)
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#define DSIM_SWRST (1 << 0)
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/* EXYNOS_DSIM_TIMEOUT */
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#define DSIM_LPDR_TOUT_SHIFT (0)
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#define DSIM_BTA_TOUT_SHIFT (16)
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/* EXYNOS_DSIM_CLKCTRL */
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#define DSIM_LANE_ESC_CLKEN_SHIFT (19)
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#define DSIM_BYTE_CLKEN_SHIFT (24)
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#define DSIM_BYTE_CLK_SRC_SHIFT (25)
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#define DSIM_PLL_BYPASS_SHIFT (27)
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#define DSIM_ESC_CLKEN_SHIFT (28)
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#define DSIM_TX_REQUEST_HSCLK_SHIFT (31)
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#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << \
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DSIM_LANE_ESC_CLKEN_SHIFT)
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#define DSIM_BYTE_CLK_ENABLE (1 << DSIM_BYTE_CLKEN_SHIFT)
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#define DSIM_BYTE_CLK_DISABLE (0 << DSIM_BYTE_CLKEN_SHIFT)
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#define DSIM_PLL_BYPASS_EXTERNAL (1 << DSIM_PLL_BYPASS_SHIFT)
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#define DSIM_ESC_CLKEN_ENABLE (1 << DSIM_ESC_CLKEN_SHIFT)
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#define DSIM_ESC_CLKEN_DISABLE (0 << DSIM_ESC_CLKEN_SHIFT)
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/* EXYNOS_DSIM_CONFIG */
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#define DSIM_NUM_OF_DATALANE_SHIFT (5)
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#define DSIM_SUBPIX_SHIFT (8)
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#define DSIM_MAINPIX_SHIFT (12)
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#define DSIM_SUBVC_SHIFT (16)
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#define DSIM_MAINVC_SHIFT (18)
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#define DSIM_HSA_MODE_SHIFT (20)
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#define DSIM_HBP_MODE_SHIFT (21)
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#define DSIM_HFP_MODE_SHIFT (22)
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#define DSIM_HSE_MODE_SHIFT (23)
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#define DSIM_AUTO_MODE_SHIFT (24)
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#define DSIM_VIDEO_MODE_SHIFT (25)
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#define DSIM_BURST_MODE_SHIFT (26)
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#define DSIM_EOT_PACKET_SHIFT (28)
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#define DSIM_AUTO_FLUSH_SHIFT (29)
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#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0)
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#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT)
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/* EXYNOS_DSIM_ESCMODE */
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#define DSIM_TX_LPDT_SHIFT (6)
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#define DSIM_CMD_LPDT_SHIFT (7)
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#define DSIM_TX_LPDT_LP (1 << DSIM_TX_LPDT_SHIFT)
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#define DSIM_CMD_LPDT_LP (1 << DSIM_CMD_LPDT_SHIFT)
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#define DSIM_STOP_STATE_CNT_SHIFT (21)
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#define DSIM_FORCE_STOP_STATE_SHIFT (20)
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/* EXYNOS_DSIM_MDRESOL */
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#define DSIM_MAIN_STAND_BY (1 << 31)
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#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
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#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
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/* EXYNOS_DSIM_MVPORCH */
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#define DSIM_CMD_ALLOW_SHIFT (28)
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#define DSIM_STABLE_VFP_SHIFT (16)
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#define DSIM_MAIN_VBP_SHIFT (0)
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#define DSIM_CMD_ALLOW_MASK (0xf << DSIM_CMD_ALLOW_SHIFT)
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#define DSIM_STABLE_VFP_MASK (0x7ff << DSIM_STABLE_VFP_SHIFT)
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#define DSIM_MAIN_VBP_MASK (0x7ff << DSIM_MAIN_VBP_SHIFT)
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/* EXYNOS_DSIM_MHPORCH */
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#define DSIM_MAIN_HFP_SHIFT (16)
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#define DSIM_MAIN_HBP_SHIFT (0)
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#define DSIM_MAIN_HFP_MASK ((0xffff) << DSIM_MAIN_HFP_SHIFT)
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#define DSIM_MAIN_HBP_MASK ((0xffff) << DSIM_MAIN_HBP_SHIFT)
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/* EXYNOS_DSIM_MSYNC */
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#define DSIM_MAIN_VSA_SHIFT (22)
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#define DSIM_MAIN_HSA_SHIFT (0)
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#define DSIM_MAIN_VSA_MASK ((0x3ff) << DSIM_MAIN_VSA_SHIFT)
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#define DSIM_MAIN_HSA_MASK ((0xffff) << DSIM_MAIN_HSA_SHIFT)
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/* EXYNOS_DSIM_SDRESOL */
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#define DSIM_SUB_STANDY_SHIFT (31)
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#define DSIM_SUB_VRESOL_SHIFT (16)
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#define DSIM_SUB_HRESOL_SHIFT (0)
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#define DSIM_SUB_STANDY_MASK ((0x1) << DSIM_SUB_STANDY_SHIFT)
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#define DSIM_SUB_VRESOL_MASK ((0x7ff) << DSIM_SUB_VRESOL_SHIFT)
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#define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT)
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/* EXYNOS_DSIM_INTSRC */
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#define INTSRC_FRAME_DONE (1 << 24)
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#define INTSRC_PLL_STABLE (1 << 31)
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#define INTSRC_SWRST_RELEASE (1 << 30)
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/* EXYNOS_DSIM_INTMSK */
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#define INTMSK_FRAME_DONE (1 << 24)
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/* EXYNOS_DSIM_FIFOCTRL */
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#define SFR_HEADER_EMPTY (1 << 22)
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/* EXYNOS_DSIM_PKTHDR */
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#define DSIM_PKTHDR_DI(x) (((x) & 0x3f) << 0)
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#define DSIM_PKTHDR_DAT0(x) ((x) << 8)
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#define DSIM_PKTHDR_DAT1(x) ((x) << 16)
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/* EXYNOS_DSIM_PHYACCHR */
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#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
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#define DSIM_AFC_CTL_SHIFT (5)
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#define DSIM_AFC_EN (1 << 14)
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/* EXYNOS_DSIM_PHYACCHR1 */
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#define DSIM_DPDN_SWAP_DATA_SHIFT (0)
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/* EXYNOS_DSIM_PLLCTRL */
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#define DSIM_SCALER_SHIFT (1)
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#define DSIM_MAIN_SHIFT (4)
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#define DSIM_PREDIV_SHIFT (13)
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#define DSIM_PRECTRL_SHIFT (20)
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#define DSIM_PLL_EN_SHIFT (23)
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#define DSIM_FREQ_BAND_SHIFT (24)
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#define DSIM_ZEROCTRL_SHIFT (28)
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#endif
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