upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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754 lines
17 KiB
754 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2011 The Chromium OS Authors.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/pinmux.h>
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/* return 1 if a pingrp is in range */
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#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
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/* return 1 if a pmux_func is in range */
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#define pmux_func_isvalid(func) \
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(((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
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/* return 1 if a pin_pupd_is in range */
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#define pmux_pin_pupd_isvalid(pupd) \
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(((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
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/* return 1 if a pin_tristate_is in range */
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#define pmux_pin_tristate_isvalid(tristate) \
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(((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
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#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
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/* return 1 if a pin_io_is in range */
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#define pmux_pin_io_isvalid(io) \
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(((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_LOCK
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/* return 1 if a pin_lock is in range */
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#define pmux_pin_lock_isvalid(lock) \
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(((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_OD
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/* return 1 if a pin_od is in range */
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#define pmux_pin_od_isvalid(od) \
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(((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
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/* return 1 if a pin_ioreset_is in range */
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#define pmux_pin_ioreset_isvalid(ioreset) \
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(((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
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((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
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/* return 1 if a pin_rcv_sel_is in range */
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#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
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(((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
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((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
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/* return 1 if a pin_e_io_hv is in range */
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#define pmux_pin_e_io_hv_isvalid(e_io_hv) \
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(((e_io_hv) >= PMUX_PIN_E_IO_HV_NORMAL) && \
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((e_io_hv) <= PMUX_PIN_E_IO_HV_HIGH))
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#endif
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#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
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#define pmux_lpmd_isvalid(lpm) \
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(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
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#endif
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#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
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#define pmux_schmt_isvalid(schmt) \
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(((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
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#endif
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#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
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#define pmux_hsm_isvalid(hsm) \
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(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
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#endif
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#define _R(offset) (u32 *)((unsigned long)NV_PA_APB_MISC_BASE + (offset))
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#if defined(CONFIG_TEGRA20)
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#define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
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#define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
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#define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
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#define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
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#define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
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#define TRI_SHIFT(grp) ((grp) % 32)
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#else
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#define REG(pin) _R(0x3000 + ((pin) * 4))
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#define MUX_REG(pin) REG(pin)
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#define MUX_SHIFT(pin) 0
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#define PULL_REG(pin) REG(pin)
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#define PULL_SHIFT(pin) 2
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#define TRI_REG(pin) REG(pin)
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#define TRI_SHIFT(pin) 4
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#endif /* CONFIG_TEGRA20 */
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#define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
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#define MIPIPADCTRL_REG(group) _R(TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG + ((group) * 4))
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/*
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* We could force arch-tegraNN/pinmux.h to define all of these. However,
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* that's a lot of defines, and for now it's manageable to just put a
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* special case here. It's possible this decision will change with future
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* SoCs.
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*/
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#ifdef CONFIG_TEGRA210
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#define IO_SHIFT 6
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#define LOCK_SHIFT 7
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#ifdef TEGRA_PMX_PINS_HAVE_HSM
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#define HSM_SHIFT 9
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#endif
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#define E_IO_HV_SHIFT 10
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#define OD_SHIFT 11
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#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
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#define SCHMT_SHIFT 12
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#endif
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#else
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#define IO_SHIFT 5
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#define OD_SHIFT 6
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#define LOCK_SHIFT 7
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#define IO_RESET_SHIFT 8
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#define RCV_SEL_SHIFT 9
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#endif
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#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
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/* This register/field only exists on Tegra114 and later */
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#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
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#define CLAMP_INPUTS_WHEN_TRISTATED 1
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void pinmux_set_tristate_input_clamping(void)
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{
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u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
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setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
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}
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void pinmux_clear_tristate_input_clamping(void)
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{
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u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
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clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
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}
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#endif
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void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
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{
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u32 *reg = MUX_REG(pin);
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int i, mux = -1;
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u32 val;
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if (func == PMUX_FUNC_DEFAULT)
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return;
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/* Error check on pin and func */
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assert(pmux_pingrp_isvalid(pin));
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assert(pmux_func_isvalid(func));
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if (func >= PMUX_FUNC_RSVD1) {
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mux = (func - PMUX_FUNC_RSVD1) & 3;
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} else {
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/* Search for the appropriate function */
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for (i = 0; i < 4; i++) {
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if (tegra_soc_pingroups[pin].funcs[i] == func) {
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mux = i;
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break;
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}
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}
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}
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assert(mux != -1);
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val = readl(reg);
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val &= ~(3 << MUX_SHIFT(pin));
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val |= (mux << MUX_SHIFT(pin));
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writel(val, reg);
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}
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void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
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{
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u32 *reg = PULL_REG(pin);
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u32 val;
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/* Error check on pin and pupd */
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assert(pmux_pingrp_isvalid(pin));
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assert(pmux_pin_pupd_isvalid(pupd));
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val = readl(reg);
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val &= ~(3 << PULL_SHIFT(pin));
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val |= (pupd << PULL_SHIFT(pin));
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writel(val, reg);
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}
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static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
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{
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u32 *reg = TRI_REG(pin);
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u32 val;
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/* Error check on pin */
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assert(pmux_pingrp_isvalid(pin));
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assert(pmux_pin_tristate_isvalid(tri));
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val = readl(reg);
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if (tri == PMUX_TRI_TRISTATE)
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val |= (1 << TRI_SHIFT(pin));
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else
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val &= ~(1 << TRI_SHIFT(pin));
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writel(val, reg);
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}
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void pinmux_tristate_enable(enum pmux_pingrp pin)
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{
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pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
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}
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void pinmux_tristate_disable(enum pmux_pingrp pin)
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{
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pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
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}
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#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
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void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
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{
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u32 *reg = REG(pin);
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u32 val;
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if (io == PMUX_PIN_NONE)
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return;
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/* Error check on pin and io */
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assert(pmux_pingrp_isvalid(pin));
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assert(pmux_pin_io_isvalid(io));
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val = readl(reg);
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if (io == PMUX_PIN_INPUT)
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val |= (io & 1) << IO_SHIFT;
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else
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val &= ~(1 << IO_SHIFT);
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writel(val, reg);
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}
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_LOCK
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static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
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{
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u32 *reg = REG(pin);
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u32 val;
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if (lock == PMUX_PIN_LOCK_DEFAULT)
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return;
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/* Error check on pin and lock */
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assert(pmux_pingrp_isvalid(pin));
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assert(pmux_pin_lock_isvalid(lock));
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val = readl(reg);
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if (lock == PMUX_PIN_LOCK_ENABLE) {
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val |= (1 << LOCK_SHIFT);
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} else {
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if (val & (1 << LOCK_SHIFT))
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printf("%s: Cannot clear LOCK bit!\n", __func__);
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val &= ~(1 << LOCK_SHIFT);
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}
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writel(val, reg);
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return;
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}
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_OD
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static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
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{
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u32 *reg = REG(pin);
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u32 val;
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if (od == PMUX_PIN_OD_DEFAULT)
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return;
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/* Error check on pin and od */
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assert(pmux_pingrp_isvalid(pin));
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assert(pmux_pin_od_isvalid(od));
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val = readl(reg);
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if (od == PMUX_PIN_OD_ENABLE)
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val |= (1 << OD_SHIFT);
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else
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val &= ~(1 << OD_SHIFT);
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writel(val, reg);
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return;
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}
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
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static void pinmux_set_ioreset(enum pmux_pingrp pin,
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enum pmux_pin_ioreset ioreset)
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{
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u32 *reg = REG(pin);
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u32 val;
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if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
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return;
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/* Error check on pin and ioreset */
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assert(pmux_pingrp_isvalid(pin));
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assert(pmux_pin_ioreset_isvalid(ioreset));
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val = readl(reg);
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if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
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val |= (1 << IO_RESET_SHIFT);
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else
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val &= ~(1 << IO_RESET_SHIFT);
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writel(val, reg);
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return;
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}
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
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static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
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enum pmux_pin_rcv_sel rcv_sel)
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{
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u32 *reg = REG(pin);
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u32 val;
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if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
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return;
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/* Error check on pin and rcv_sel */
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assert(pmux_pingrp_isvalid(pin));
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assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
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val = readl(reg);
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if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
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val |= (1 << RCV_SEL_SHIFT);
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else
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val &= ~(1 << RCV_SEL_SHIFT);
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writel(val, reg);
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return;
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}
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
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static void pinmux_set_e_io_hv(enum pmux_pingrp pin,
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enum pmux_pin_e_io_hv e_io_hv)
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{
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u32 *reg = REG(pin);
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u32 val;
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if (e_io_hv == PMUX_PIN_E_IO_HV_DEFAULT)
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return;
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/* Error check on pin and e_io_hv */
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assert(pmux_pingrp_isvalid(pin));
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assert(pmux_pin_e_io_hv_isvalid(e_io_hv));
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val = readl(reg);
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if (e_io_hv == PMUX_PIN_E_IO_HV_HIGH)
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val |= (1 << E_IO_HV_SHIFT);
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else
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val &= ~(1 << E_IO_HV_SHIFT);
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writel(val, reg);
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return;
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}
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
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static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt)
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{
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u32 *reg = REG(grp);
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u32 val;
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/* NONE means unspecified/do not change/use POR value */
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if (schmt == PMUX_SCHMT_NONE)
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return;
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/* Error check pad */
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assert(pmux_pingrp_isvalid(pin));
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assert(pmux_schmt_isvalid(schmt));
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val = readl(reg);
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if (schmt == PMUX_SCHMT_ENABLE)
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val |= (1 << SCHMT_SHIFT);
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else
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val &= ~(1 << SCHMT_SHIFT);
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writel(val, reg);
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return;
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}
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_HSM
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static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm)
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{
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u32 *reg = REG(grp);
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u32 val;
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/* NONE means unspecified/do not change/use POR value */
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if (hsm == PMUX_HSM_NONE)
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return;
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/* Error check pad */
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assert(pmux_pingrp_isvalid(pin));
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assert(pmux_hsm_isvalid(hsm));
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val = readl(reg);
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if (hsm == PMUX_HSM_ENABLE)
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val |= (1 << HSM_SHIFT);
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else
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val &= ~(1 << HSM_SHIFT);
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writel(val, reg);
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return;
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}
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#endif
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static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
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{
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enum pmux_pingrp pin = config->pingrp;
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pinmux_set_func(pin, config->func);
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pinmux_set_pullupdown(pin, config->pull);
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pinmux_set_tristate(pin, config->tristate);
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#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
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pinmux_set_io(pin, config->io);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_LOCK
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pinmux_set_lock(pin, config->lock);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_OD
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pinmux_set_od(pin, config->od);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
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pinmux_set_ioreset(pin, config->ioreset);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
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pinmux_set_rcv_sel(pin, config->rcv_sel);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
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pinmux_set_e_io_hv(pin, config->e_io_hv);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
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pinmux_set_schmt(pin, config->schmt);
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_HSM
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pinmux_set_hsm(pin, config->hsm);
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#endif
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}
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void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
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int len)
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{
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int i;
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for (i = 0; i < len; i++)
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pinmux_config_pingrp(&config[i]);
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}
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#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
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#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
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#define pmux_slw_isvalid(slw) \
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(((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
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#define pmux_drv_isvalid(drv) \
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(((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
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#ifdef TEGRA_PMX_GRPS_HAVE_HSM
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#define HSM_SHIFT 2
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#endif
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#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
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#define SCHMT_SHIFT 3
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#endif
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#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
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#define LPMD_SHIFT 4
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#define LPMD_MASK (3 << LPMD_SHIFT)
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#endif
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/*
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* Note that the following DRV* and SLW* defines are accurate for many drive
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* groups on many SoCs. We really need a per-group data structure to solve
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* this, since the fields are in different positions/sizes in different
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|
* registers (for different groups).
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*
|
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* On Tegra30/114/124, the DRV*_SHIFT values vary.
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* On Tegra30, the SLW*_SHIFT values vary.
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* On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
|
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* below are wide enough to cover the widest fields, and hopefully don't
|
|
* interfere with any other fields.
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* On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
|
|
* wide enough to cover all cases, since that would cause the field to
|
|
* overlap with other fields in the narrower cases.
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|
*/
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#define DRVDN_SHIFT 12
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#define DRVDN_MASK (0x7F << DRVDN_SHIFT)
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#define DRVUP_SHIFT 20
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#define DRVUP_MASK (0x7F << DRVUP_SHIFT)
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#define SLWR_SHIFT 28
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#define SLWR_MASK (3 << SLWR_SHIFT)
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#define SLWF_SHIFT 30
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#define SLWF_MASK (3 << SLWF_SHIFT)
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|
|
|
static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
|
|
{
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|
u32 *reg = DRV_REG(grp);
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u32 val;
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|
|
|
/* NONE means unspecified/do not change/use POR value */
|
|
if (slwf == PMUX_SLWF_NONE)
|
|
return;
|
|
|
|
/* Error check on pad and slwf */
|
|
assert(pmux_drvgrp_isvalid(grp));
|
|
assert(pmux_slw_isvalid(slwf));
|
|
|
|
val = readl(reg);
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|
val &= ~SLWF_MASK;
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|
val |= (slwf << SLWF_SHIFT);
|
|
writel(val, reg);
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|
|
|
return;
|
|
}
|
|
|
|
static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
|
|
{
|
|
u32 *reg = DRV_REG(grp);
|
|
u32 val;
|
|
|
|
/* NONE means unspecified/do not change/use POR value */
|
|
if (slwr == PMUX_SLWR_NONE)
|
|
return;
|
|
|
|
/* Error check on pad and slwr */
|
|
assert(pmux_drvgrp_isvalid(grp));
|
|
assert(pmux_slw_isvalid(slwr));
|
|
|
|
val = readl(reg);
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|
val &= ~SLWR_MASK;
|
|
val |= (slwr << SLWR_SHIFT);
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|
writel(val, reg);
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|
|
|
return;
|
|
}
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|
|
|
static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
|
|
{
|
|
u32 *reg = DRV_REG(grp);
|
|
u32 val;
|
|
|
|
/* NONE means unspecified/do not change/use POR value */
|
|
if (drvup == PMUX_DRVUP_NONE)
|
|
return;
|
|
|
|
/* Error check on pad and drvup */
|
|
assert(pmux_drvgrp_isvalid(grp));
|
|
assert(pmux_drv_isvalid(drvup));
|
|
|
|
val = readl(reg);
|
|
val &= ~DRVUP_MASK;
|
|
val |= (drvup << DRVUP_SHIFT);
|
|
writel(val, reg);
|
|
|
|
return;
|
|
}
|
|
|
|
static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
|
|
{
|
|
u32 *reg = DRV_REG(grp);
|
|
u32 val;
|
|
|
|
/* NONE means unspecified/do not change/use POR value */
|
|
if (drvdn == PMUX_DRVDN_NONE)
|
|
return;
|
|
|
|
/* Error check on pad and drvdn */
|
|
assert(pmux_drvgrp_isvalid(grp));
|
|
assert(pmux_drv_isvalid(drvdn));
|
|
|
|
val = readl(reg);
|
|
val &= ~DRVDN_MASK;
|
|
val |= (drvdn << DRVDN_SHIFT);
|
|
writel(val, reg);
|
|
|
|
return;
|
|
}
|
|
|
|
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
|
|
static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
|
|
{
|
|
u32 *reg = DRV_REG(grp);
|
|
u32 val;
|
|
|
|
/* NONE means unspecified/do not change/use POR value */
|
|
if (lpmd == PMUX_LPMD_NONE)
|
|
return;
|
|
|
|
/* Error check pad and lpmd value */
|
|
assert(pmux_drvgrp_isvalid(grp));
|
|
assert(pmux_lpmd_isvalid(lpmd));
|
|
|
|
val = readl(reg);
|
|
val &= ~LPMD_MASK;
|
|
val |= (lpmd << LPMD_SHIFT);
|
|
writel(val, reg);
|
|
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
|
|
static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
|
|
{
|
|
u32 *reg = DRV_REG(grp);
|
|
u32 val;
|
|
|
|
/* NONE means unspecified/do not change/use POR value */
|
|
if (schmt == PMUX_SCHMT_NONE)
|
|
return;
|
|
|
|
/* Error check pad */
|
|
assert(pmux_drvgrp_isvalid(grp));
|
|
assert(pmux_schmt_isvalid(schmt));
|
|
|
|
val = readl(reg);
|
|
if (schmt == PMUX_SCHMT_ENABLE)
|
|
val |= (1 << SCHMT_SHIFT);
|
|
else
|
|
val &= ~(1 << SCHMT_SHIFT);
|
|
writel(val, reg);
|
|
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
|
|
static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
|
|
{
|
|
u32 *reg = DRV_REG(grp);
|
|
u32 val;
|
|
|
|
/* NONE means unspecified/do not change/use POR value */
|
|
if (hsm == PMUX_HSM_NONE)
|
|
return;
|
|
|
|
/* Error check pad */
|
|
assert(pmux_drvgrp_isvalid(grp));
|
|
assert(pmux_hsm_isvalid(hsm));
|
|
|
|
val = readl(reg);
|
|
if (hsm == PMUX_HSM_ENABLE)
|
|
val |= (1 << HSM_SHIFT);
|
|
else
|
|
val &= ~(1 << HSM_SHIFT);
|
|
writel(val, reg);
|
|
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
|
|
{
|
|
enum pmux_drvgrp grp = config->drvgrp;
|
|
|
|
pinmux_set_drvup_slwf(grp, config->slwf);
|
|
pinmux_set_drvdn_slwr(grp, config->slwr);
|
|
pinmux_set_drvup(grp, config->drvup);
|
|
pinmux_set_drvdn(grp, config->drvdn);
|
|
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
|
|
pinmux_set_lpmd(grp, config->lpmd);
|
|
#endif
|
|
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
|
|
pinmux_set_schmt(grp, config->schmt);
|
|
#endif
|
|
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
|
|
pinmux_set_hsm(grp, config->hsm);
|
|
#endif
|
|
}
|
|
|
|
void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
|
|
int len)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < len; i++)
|
|
pinmux_config_drvgrp(&config[i]);
|
|
}
|
|
#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
|
|
|
|
#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
|
|
|
|
#define pmux_mipipadctrlgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_MIPIPADCTRLGRP_COUNT))
|
|
|
|
static void pinmux_mipipadctrl_set_func(enum pmux_mipipadctrlgrp grp,
|
|
enum pmux_func func)
|
|
{
|
|
u32 *reg = MIPIPADCTRL_REG(grp);
|
|
int i, mux = -1;
|
|
u32 val;
|
|
|
|
if (func == PMUX_FUNC_DEFAULT)
|
|
return;
|
|
|
|
/* Error check grp and func */
|
|
assert(pmux_mipipadctrlgrp_isvalid(grp));
|
|
assert(pmux_func_isvalid(func));
|
|
|
|
if (func >= PMUX_FUNC_RSVD1) {
|
|
mux = (func - PMUX_FUNC_RSVD1) & 1;
|
|
} else {
|
|
/* Search for the appropriate function */
|
|
for (i = 0; i < 2; i++) {
|
|
if (tegra_soc_mipipadctrl_groups[grp].funcs[i]
|
|
== func) {
|
|
mux = i;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
assert(mux != -1);
|
|
|
|
val = readl(reg);
|
|
val &= ~(1 << 1);
|
|
val |= (mux << 1);
|
|
writel(val, reg);
|
|
}
|
|
|
|
static void pinmux_config_mipipadctrlgrp(const struct pmux_mipipadctrlgrp_config *config)
|
|
{
|
|
enum pmux_mipipadctrlgrp grp = config->grp;
|
|
|
|
pinmux_mipipadctrl_set_func(grp, config->func);
|
|
}
|
|
|
|
void pinmux_config_mipipadctrlgrp_table(
|
|
const struct pmux_mipipadctrlgrp_config *config, int len)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < len; i++)
|
|
pinmux_config_mipipadctrlgrp(&config[i]);
|
|
}
|
|
#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
|
|
|