upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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173 lines
5.1 KiB
173 lines
5.1 KiB
/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */
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/*
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* (C) Copyright 2002-2003
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* Josef Wagner, MicroSys GmbH, wagner@microsys.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Date Modification by
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* ------- ---------------------------------------------- ---
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* 30sep02 converted from VxWorks to LINUX wa
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*/
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/*
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DESCRIPTION
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This is the configuration module for the PLX9030 PCI to Local Bus Bridge.
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It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local
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registers (CS3) on CPC45.
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*/
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/* includes */
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <asm/io.h>
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#include <pci.h>
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/* imports */
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/* defines */
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#define PLX9030_VENDOR_ID 0x10B5
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#define PLX9030_DEVICE_ID 0x9030
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#undef PLX_DEBUG
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/* PLX9030 register offsets */
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#define P9030_LAS0RR 0x00
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#define P9030_LAS1RR 0x04
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#define P9030_LAS2RR 0x08
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#define P9030_LAS3RR 0x0c
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#define P9030_EROMRR 0x10
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#define P9030_LAS0BA 0x14
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#define P9030_LAS1BA 0x18
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#define P9030_LAS2BA 0x1c
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#define P9030_LAS3BA 0x20
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#define P9030_EROMBA 0x24
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#define P9030_LAS0BRD 0x28
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#define P9030_LAS1BRD 0x2c
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#define P9030_LAS2BRD 0x30
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#define P9030_LAS3BRD 0x34
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#define P9030_EROMBRD 0x38
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#define P9030_CS0BASE 0x3C
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#define P9030_CS1BASE 0x40
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#define P9030_CS2BASE 0x44
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#define P9030_CS3BASE 0x48
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#define P9030_INTCSR 0x4c
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#define P9030_CNTRL 0x50
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#define P9030_GPIOC 0x54
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/* typedefs */
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/* locals */
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static struct pci_device_id supported[] = {
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{ PLX9030_VENDOR_ID, PLX9030_DEVICE_ID },
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{ }
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};
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/* forward declarations */
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void sysOutLong(ulong address, ulong value);
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/***************************************************************************
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*
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* Plx9030Init - init CS0..CS3 for CPC45
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*
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*
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* RETURNS: N/A
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*/
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void Plx9030Init (void)
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{
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pci_dev_t devno;
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ulong membaseCsr; /* base address of device memory space */
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int idx = 0; /* general index */
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/* find plx9030 device */
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if ((devno = pci_find_devices(supported, idx++)) < 0)
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{
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printf("No PLX9030 device found !!\n");
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return;
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}
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#ifdef PLX_DEBUG
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printf("PLX 9030 device found ! devno = 0x%x\n",devno);
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#endif
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membaseCsr = PCI_PLX9030_MEMADDR;
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/* set base address */
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pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr);
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/* enable mapped memory and IO addresses */
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pci_write_config_dword(devno,
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PCI_COMMAND,
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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/* configure GBIOC */
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sysOutLong((membaseCsr + P9030_GPIOC), 0x00000FC0); /* CS2/CS3 enable */
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/* configure CS0 (SRAM) */
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sysOutLong((membaseCsr + P9030_LAS0BA), 0x00000001); /* enable space base */
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sysOutLong((membaseCsr + P9030_LAS0RR), 0x0FE00000); /* 2 MByte */
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sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900); /* 4 wait states */
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sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001); /* enable 2 MByte */
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/* remap CS0 (SRAM) */
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pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE);
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/* configure CS1 (ST16552 / CHAN A) */
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sysOutLong((membaseCsr + P9030_LAS1BA), 0x00400001); /* enable space base */
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sysOutLong((membaseCsr + P9030_LAS1RR), 0x0FFFFF00); /* 256 byte */
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sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900); /* 4 wait states */
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sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081); /* enable 256 Byte */
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/* remap CS1 (ST16552 / CHAN A) */
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/* remap CS1 (ST16552 / CHAN A) */
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pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE);
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/* configure CS2 (ST16552 / CHAN B) */
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sysOutLong((membaseCsr + P9030_LAS2BA), 0x00800001); /* enable space base */
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sysOutLong((membaseCsr + P9030_LAS2RR), 0x0FFFFF00); /* 256 byte */
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sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900); /* 4 wait states */
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sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081); /* enable 256 Byte */
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/* remap CS2 (ST16552 / CHAN B) */
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pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE);
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/* configure CS3 (BCSR) */
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sysOutLong((membaseCsr + P9030_LAS3BA), 0x00C00001); /* enable space base */
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sysOutLong((membaseCsr + P9030_LAS3RR), 0x0FFFFF00); /* 256 byte */
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sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80); /* 9 wait states */
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sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081); /* enable 256 Byte */
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/* remap CS3 (DISPLAY and BCSR) */
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pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE);
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}
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void sysOutLong(ulong address, ulong value)
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{
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*(ulong*)address = cpu_to_le32(value);
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}
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