upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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49 lines
1.7 KiB
49 lines
1.7 KiB
/**
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* Copyright 2014 Freescale Semiconductor
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*
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* Author: Chunhe Lan <Chunhe.Lan@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* This file provides support for the ngPIXIS, a board-specific FPGA used on
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* some Freescale reference boards.
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*/
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/*
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* CPLD register set. Feel free to add board-specific #ifdefs where necessary.
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*/
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struct cpld_data {
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u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */
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u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */
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u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */
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u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */
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u8 hw_ver; /* 0x04 - PCBA Version Register */
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u8 software_on; /* 0x05 - Override Physical Switch Enable Register */
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u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */
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u8 res0; /* 0x07 - not used */
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u8 vbank; /* 0x08 - Flash Bank Selection Control Register */
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u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */
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u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */
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u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */
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u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */
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u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/
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u8 global_reset;/* 0x0e - Reset System With Default Registers Value */
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u8 res1; /* 0x0f - not used */
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};
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#define CPLD_BANK_SEL_MASK 0x07
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#define CPLD_BANK_SEL_EN 0x04
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#define CPLD_SYSTEM_RESET 0x01
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#define CPLD_SELECT_BANK0 0x00
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#define CPLD_SELECT_BANK4 0x04
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#define CPLD_DEFAULT_BANK 0x01
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/* Pointer to the CPLD register set */
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u8 cpld_read(unsigned int reg);
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void cpld_write(unsigned int reg, u8 value);
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
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#define CPLD_WRITE(reg, value) \
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cpld_write(offsetof(struct cpld_data, reg), value)
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