upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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420 lines
12 KiB
420 lines
12 KiB
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CONFIG_PCI
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#include <pci.h>
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#include <mpc8260.h>
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#include <asm/m8260_pci.h>
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#include <asm/io.h>
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/*
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* Local->PCI map (from CPU) controlled by
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* MPC826x master window
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*
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* 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
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* 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
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*
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* 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
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* PCI Mem with prefetch
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*
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* 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
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* PCI Mem w/o prefetch
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*
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* 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
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* 32-bit PCI IO
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*
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* PCI->Local map (from PCI)
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* MPC826x slave window controlled by
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*
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* 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
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* MPC826x local memory
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*/
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/*
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* Slave window that allows PCI masters to access MPC826x local memory.
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* This window is set up using the first set of Inbound ATU registers
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*/
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#ifndef CFG_PCI_SLV_MEM_LOCAL
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#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
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#else
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#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
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#endif
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#ifndef CFG_PCI_SLV_MEM_BUS
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#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
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#else
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#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
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#endif
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#ifndef CFG_PICMR0_MASK_ATTRIB
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#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
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PICMR_PREFETCH_EN)
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#else
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#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
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#endif
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/*
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* These are the windows that allow the CPU to access PCI address space.
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* All three PCI master windows, which allow the CPU to access PCI
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* prefetch, non prefetch, and IO space (see below), must all fit within
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* these windows.
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*/
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/* PCIBR0 */
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#ifndef CFG_PCI_MSTR0_LOCAL
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#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
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#else
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#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
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#endif
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#ifndef CFG_PCIMSK0_MASK
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#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
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#else
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#define PCIMSK0_MASK CFG_PCIMSK0_MASK
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#endif
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/* PCIBR1 */
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#ifndef CFG_PCI_MSTR1_LOCAL
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#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
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#else
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#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
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#endif
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#ifndef CFG_PCIMSK1_MASK
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#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
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#else
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#define PCIMSK1_MASK CFG_PCIMSK1_MASK
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#endif
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/*
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* Master window that allows the CPU to access PCI Memory (prefetch).
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* This window will be setup with the first set of Outbound ATU registers
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* in the bridge.
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*/
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#ifndef CFG_PCI_MSTR_MEM_LOCAL
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#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
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#else
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#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
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#endif
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#ifndef CFG_PCI_MSTR_MEM_BUS
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#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
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#else
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#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
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#endif
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#ifndef CFG_CPU_PCI_MEM_START
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#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
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#else
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#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
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#endif
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#ifndef CFG_PCI_MSTR_MEM_SIZE
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#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
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#else
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#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
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#endif
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#ifndef CFG_POCMR0_MASK_ATTRIB
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#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
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#else
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#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
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#endif
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/*
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* Master window that allows the CPU to access PCI Memory (non-prefetch).
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* This window will be setup with the second set of Outbound ATU registers
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* in the bridge.
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*/
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#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
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#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
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#else
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#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
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#endif
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#ifndef CFG_PCI_MSTR_MEMIO_BUS
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#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
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#else
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#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
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#endif
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#ifndef CFG_CPU_PCI_MEMIO_START
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#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
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#else
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#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
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#endif
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#ifndef CFG_PCI_MSTR_MEMIO_SIZE
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#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
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#else
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#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
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#endif
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#ifndef CFG_POCMR1_MASK_ATTRIB
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#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
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#else
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#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
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#endif
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/*
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* Master window that allows the CPU to access PCI IO space.
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* This window will be setup with the third set of Outbound ATU registers
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* in the bridge.
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*/
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#ifndef CFG_PCI_MSTR_IO_LOCAL
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#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
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#else
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#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
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#endif
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#ifndef CFG_PCI_MSTR_IO_BUS
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#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
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#else
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#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
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#endif
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#ifndef CFG_CPU_PCI_IO_START
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#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
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#else
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#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
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#endif
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#ifndef CFG_PCI_MSTR_IO_SIZE
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#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
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#else
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#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
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#endif
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#ifndef CFG_POCMR2_MASK_ATTRIB
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#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
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#else
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#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
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#endif
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/* PCI bus configuration registers.
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*/
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#define PCI_CLASS_BRIDGE_CTLR 0x06
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static inline void pci_outl (u32 addr, u32 data)
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{
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*(volatile u32 *) addr = cpu_to_le32 (data);
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}
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void pci_mpc8250_init (struct pci_controller *hose)
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{
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#ifdef CONFIG_MPC8266ADS
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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u16 tempShort;
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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pci_dev_t host_devno = PCI_BDF (0, 0, 0);
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pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
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CFG_IMMR + PCI_CFG_DATA_REG);
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/*
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* Setting required to enable local bus for PCI (SIUMCR [LBPC]).
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*/
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#ifdef CONFIG_MPC8266ADS
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immap->im_siu_conf.sc_siumcr =
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(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
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| SIUMCR_LBPC01;
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#else
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/*
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* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
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* and local bus for PCI (SIUMCR [LBPC]).
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*/
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immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
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~SIUMCR_LBPC11 &
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~SIUMCR_CS10PC11 &
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~SIUMCR_LBPC11) |
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SIUMCR_LBPC01 |
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SIUMCR_CS10PC01 |
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SIUMCR_APPC10;
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#endif
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/* Make PCI lowest priority */
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/* Each 4 bits is a device bus request and the MS 4bits
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is highest priority */
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/* Bus 4bit value
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--- ----------
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CPM high 0b0000
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CPM middle 0b0001
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CPM low 0b0010
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PCI reguest 0b0011
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Reserved 0b0100
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Reserved 0b0101
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Internal Core 0b0110
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External Master 1 0b0111
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External Master 2 0b1000
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External Master 3 0b1001
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The rest are reserved */
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immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
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/* Park bus on core while modifying PCI Bus accesses */
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immap->im_siu_conf.sc_ppc_acr = 0x6;
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/*
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* Set up master windows that allow the CPU to access PCI space. These
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* windows are set up using the two SIU PCIBR registers.
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*/
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immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
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immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
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#ifdef CONFIG_MPC8266ADS
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immap->im_memctl.memc_pcimsk0 = PCIMSK1_MASK;
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immap->im_memctl.memc_pcibr0 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
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#endif
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/* Release PCI RST (by default the PCI RST signal is held low) */
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immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
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/* give it some time */
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{
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#ifdef CONFIG_MPC8266ADS
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/* Give the PCI cards more time to initialize before query
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This might be good for other boards also
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*/
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int i;
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for (i = 0; i < 1000; ++i)
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#endif
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udelay (1000);
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}
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/*
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* Set up master window that allows the CPU to access PCI Memory (prefetch)
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* space. This window is set up using the first set of Outbound ATU registers.
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*/
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immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
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immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
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immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
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/*
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* Set up master window that allows the CPU to access PCI Memory (non-prefetch)
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* space. This window is set up using the second set of Outbound ATU registers.
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*/
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immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
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immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
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immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
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/*
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* Set up master window that allows the CPU to access PCI IO space. This window
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* is set up using the third set of Outbound ATU registers.
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*/
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immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
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immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
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immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
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/*
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* Set up slave window that allows PCI masters to access MPC826x local memory.
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* This window is set up using the first set of Inbound ATU registers
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*/
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immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
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immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
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immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
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/* See above for description - puts PCI request as highest priority */
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immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
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/* Park the bus on the PCI */
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immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
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/* Host mode - specify the bridge as a host-PCI bridge */
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pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
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PCI_CLASS_BRIDGE_CTLR);
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/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
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pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
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pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
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tempShort | PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY);
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/* do some bridge init, should be done on all 8260 based bridges */
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pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
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0x08);
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pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
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0xF8);
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* System memory space */
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#ifdef CONFIG_MPC8266ADS
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pci_set_region (hose->regions + 0,
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PCI_SLV_MEM_BUS,
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PCI_SLV_MEM_LOCAL,
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gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
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#else
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pci_set_region (hose->regions + 0,
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CFG_SDRAM_BASE,
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CFG_SDRAM_BASE,
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0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
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#endif
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/* PCI memory space */
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#ifdef CONFIG_MPC8266ADS
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pci_set_region (hose->regions + 1,
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PCI_MSTR_MEMIO_BUS,
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PCI_MSTR_MEMIO_LOCAL,
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PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
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#else
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pci_set_region (hose->regions + 1,
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PCI_MSTR_MEM_BUS,
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PCI_MSTR_MEM_LOCAL,
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PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
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#endif
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/* PCI I/O space */
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pci_set_region (hose->regions + 2,
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PCI_MSTR_IO_BUS,
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PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
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hose->region_count = 3;
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pci_register_hose (hose);
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/* Mask off master abort machine checks */
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immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
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eieio ();
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hose->last_busno = pci_hose_scan (hose);
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/* clear the error in the error status register */
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immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
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/* unmask master abort machine checks */
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immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
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}
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#endif /* CONFIG_PCI */
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