upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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233 lines
7.6 KiB
233 lines
7.6 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2000
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* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
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*/
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#ifndef _NS87308_H_
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#define _NS87308_H_
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#include <asm/pci_io.h>
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/* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
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functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
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void initialise_ns87308(void);
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/*
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* The following struct represents the GPIO registers on the NS87308/NS97307
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*/
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struct GPIO
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{
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unsigned char dta1; /* 0 data port 1 */
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unsigned char dir1; /* 1 direction port 1 */
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unsigned char out1; /* 2 output type port 1 */
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unsigned char puc1; /* 3 pull-up control port 1 */
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unsigned char dta2; /* 4 data port 2 */
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unsigned char dir2; /* 5 direction port 2 */
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unsigned char out2; /* 6 output type port 2 */
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unsigned char puc2; /* 7 pull-up control port 2 */
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};
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/*
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* The following represents the power management registers on the NS87308/NS97307
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*/
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#define PWM_FER1 0 /* 0 function enable reg. 1 */
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#define PWM_FER2 1 /* 1 function enable reg. 2 */
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#define PWM_PMC1 2 /* 2 power mgmt. control 1 */
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#define PWM_PMC2 3 /* 3 power mgmt. control 2 */
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#define PWM_PMC3 4 /* 4 power mgmt. control 3 */
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#define PWM_WDTO 5 /* 5 watchdog time-out */
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#define PWM_WDCF 6 /* 6 watchdog config. */
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#define PWM_WDST 7 /* 7 watchdog status */
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/*PNP config registers:
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* these depend on the stated of BADDR1 and BADDR0 on startup
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* so there's three versions here with the last two digits indicating
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* for which configuration their valid
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* the 1st of the two digits indicates the state of BADDR1
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* the 2st of the two digits indicates the state of BADDR0
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*/
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#define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */
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#define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */
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#define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */
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#define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */
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#define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */
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#define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */
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#if defined(CONFIG_SYS_NS87308_BADDR_0x)
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#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
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#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
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#elif defined(CONFIG_SYS_NS87308_BADDR_10)
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#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
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#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
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#elif defined(CONFIG_SYS_NS87308_BADDR_11)
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#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
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#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
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#endif
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/* PnP register definitions */
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#define SET_RD_DATA_PORT 0x00
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#define SERIAL_ISOLATION 0x01
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#define CONFIG_CONTROL 0x02
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#define WAKE_CSN 0x03
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#define RES_DATA 0x04
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#define STATUS 0x05
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#define SET_CSN 0x06
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#define LOGICAL_DEVICE 0x07
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/*vendor defined values */
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#define SID_REG 0x20
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#define SUPOERIO_CONF1 0x21
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#define SUPOERIO_CONF2 0x22
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#define PGCS_INDEX 0x23
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#define PGCS_DATA 0x24
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/* values above 30 are different for each logical device
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but I can't be arsed to enter them all. the ones here
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are pretty consistent between all logical devices
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feel free to correct the situation if you want.. ;)
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*/
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#define ACTIVATE 0x30
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#define ACTIVATE_OFF 0x00
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#define ACTIVATE_ON 0x01
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#define BASE_ADDR_HIGH 0x60
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#define BASE_ADDR_LOW 0x61
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#define LUN_CONFIG_REG 0xF0
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#define DBASE_HIGH 0x60 /* SIO KBC data base address, 15:8 */
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#define DBASE_LOW 0x61 /* SIO KBC data base address, 7:0 */
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#define CBASE_HIGH 0x62 /* SIO KBC command base addr, 15:8 */
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#define CBASE_LOW 0x63 /* SIO KBC command base addr, 7:0 */
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/* the logical devices*/
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#define LDEV_KBC1 0x00 /* 2 devices for keyboard and mouse controller*/
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#define LDEV_KBC2 0x01
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#define LDEV_MOUSE 0x01
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#define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/
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#define LDEV_FDC 0x03 /*floppy disk controller*/
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#define LDEV_PARP 0x04 /*Parallel port*/
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#define LDEV_UART2 0x05
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#define LDEV_UART1 0x06
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#define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/
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#define LDEV_POWRMAN 0x08 /*Power Managment*/
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#define CONFIG_SYS_NS87308_KBC1 (1 << LDEV_KBC1)
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#define CONFIG_SYS_NS87308_KBC2 (1 << LDEV_KBC2)
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#define CONFIG_SYS_NS87308_MOUSE (1 << LDEV_MOUSE)
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#define CONFIG_SYS_NS87308_RTC_APC (1 << LDEV_RTC_APC)
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#define CONFIG_SYS_NS87308_FDC (1 << LDEV_FDC)
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#define CONFIG_SYS_NS87308_PARP (1 << LDEV_PARP)
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#define CONFIG_SYS_NS87308_UART2 (1 << LDEV_UART2)
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#define CONFIG_SYS_NS87308_UART1 (1 << LDEV_UART1)
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#define CONFIG_SYS_NS87308_GPIO (1 << LDEV_GPIO)
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#define CONFIG_SYS_NS87308_POWRMAN (1 << LDEV_POWRMAN)
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/*some functions and macro's for doing configuration */
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static inline void read_pnp_config(unsigned char index, unsigned char *data)
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{
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pci_writeb(index,IO_INDEX);
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pci_readb(IO_DATA, *data);
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}
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static inline void write_pnp_config(unsigned char index, unsigned char data)
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{
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pci_writeb(index,IO_INDEX);
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pci_writeb(data, IO_DATA);
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}
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static inline void pnp_set_device(unsigned char dev)
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{
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write_pnp_config(LOGICAL_DEVICE, dev);
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}
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static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
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{
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pci_writeb(index, CONFIG_SYS_ISA_IO + base);
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eieio();
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pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
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}
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/*void write_pnp_config(unsigned char index, unsigned char data);
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void pnp_set_device(unsigned char dev);
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*/
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#define PNP_SET_DEVICE_BASE(dev,base) \
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pnp_set_device(dev); \
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write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
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write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
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write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
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write_pnp_config(ACTIVATE, ACTIVATE_ON);
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#define PNP_ACTIVATE_DEVICE(dev) \
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pnp_set_device(dev); \
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write_pnp_config(ACTIVATE, ACTIVATE_ON);
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#define PNP_DEACTIVATE_DEVICE(dev) \
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pnp_set_device(dev); \
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write_pnp_config(ACTIVATE, ACTIVATE_OFF);
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static inline void write_pgcs_config(unsigned char index, unsigned char data)
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{
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write_pnp_config(PGCS_INDEX, index);
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write_pnp_config(PGCS_DATA, data);
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}
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/* these macrose configure the 3 CS lines
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on the sandpoint board these controll NVRAM
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CS0 is connected to NVRAMCS
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CS1 is connected to NVRAMAS0
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CS2 is connected to NVRAMAS1
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*/
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#define PGCS_CS_ASSERT_ON_WRITE 0x10
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#define PGCS_CS_ASSERT_ON_READ 0x20
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#define PNP_PGCS_CSLINE_BASE(cs, base) \
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write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
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write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
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#define PNP_PGCS_CSLINE_CONF(cs, conf) \
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write_pgcs_config(((cs) << 2) + 2, (conf) );
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/* The following sections are for 87308 extensions to the standard compoents it emulates */
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/* extensions to 16550*/
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#define MCR_MDSL_MSK 0xe0 /*mode select mask*/
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#define MCR_MDSL_UART 0x00 /*uart, default*/
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#define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
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#define MCR_MDSL_SIR 0x03 /*SIR*/
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#define MCR_MDSL_CIR 0x06 /*Consumer IR*/
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#define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */
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#define FCR_TXFTH1 0x20 /* for interrupt trigger */
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/*
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* Default NS87308 configuration
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*/
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#ifndef CONFIG_SYS_NS87308_KBC1_BASE
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#define CONFIG_SYS_NS87308_KBC1_BASE 0x0060
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#endif
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#ifndef CONFIG_SYS_NS87308_RTC_BASE
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#define CONFIG_SYS_NS87308_RTC_BASE 0x0070
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#endif
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#ifndef CONFIG_SYS_NS87308_FDC_BASE
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#define CONFIG_SYS_NS87308_FDC_BASE 0x03F0
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#endif
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#ifndef CONFIG_SYS_NS87308_LPT_BASE
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#define CONFIG_SYS_NS87308_LPT_BASE 0x0278
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#endif
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#ifndef CONFIG_SYS_NS87308_UART1_BASE
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#define CONFIG_SYS_NS87308_UART1_BASE 0x03F8
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#endif
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#ifndef CONFIG_SYS_NS87308_UART2_BASE
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#define CONFIG_SYS_NS87308_UART2_BASE 0x02F8
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#endif
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#endif /*_NS87308_H_*/
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