upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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171 lines
5.7 KiB
171 lines
5.7 KiB
/*
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* Driver for Blackfin on-chip ATAPI controller.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (c) 2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef PATA_BFIN_H
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#define PATA_BFIN_H
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#include <asm/blackfin_local.h>
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struct ata_ioports {
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unsigned long cmd_addr;
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unsigned long data_addr;
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unsigned long error_addr;
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unsigned long feature_addr;
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unsigned long nsect_addr;
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unsigned long lbal_addr;
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unsigned long lbam_addr;
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unsigned long lbah_addr;
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unsigned long device_addr;
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unsigned long status_addr;
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unsigned long command_addr;
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unsigned long altstatus_addr;
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unsigned long ctl_addr;
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unsigned long bmdma_addr;
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unsigned long scr_addr;
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};
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struct ata_port {
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unsigned int port_no; /* primary=0, secondary=1 */
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struct ata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
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unsigned long flag;
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unsigned int ata_mode;
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unsigned char ctl_reg;
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unsigned char last_ctl;
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unsigned char dev_mask;
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};
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#define DRV_NAME "pata-bfin"
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#define DRV_VERSION "0.9"
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#define __iomem
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#define ATA_REG_CTRL 0x0E
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#define ATA_REG_ALTSTATUS ATA_REG_CTRL
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#define ATA_TMOUT_BOOT 30000
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#define ATA_TMOUT_BOOT_QUICK 7000
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#define PATA_BFIN_WAIT_TIMEOUT 10000
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#define PATA_DEV_NUM_PER_PORT 2
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/* These are the offset of the controller's registers */
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#define ATAPI_OFFSET_CONTROL 0x00
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#define ATAPI_OFFSET_STATUS 0x04
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#define ATAPI_OFFSET_DEV_ADDR 0x08
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#define ATAPI_OFFSET_DEV_TXBUF 0x0c
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#define ATAPI_OFFSET_DEV_RXBUF 0x10
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#define ATAPI_OFFSET_INT_MASK 0x14
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#define ATAPI_OFFSET_INT_STATUS 0x18
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#define ATAPI_OFFSET_XFER_LEN 0x1c
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#define ATAPI_OFFSET_LINE_STATUS 0x20
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#define ATAPI_OFFSET_SM_STATE 0x24
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#define ATAPI_OFFSET_TERMINATE 0x28
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#define ATAPI_OFFSET_PIO_TFRCNT 0x2c
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#define ATAPI_OFFSET_DMA_TFRCNT 0x30
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#define ATAPI_OFFSET_UMAIN_TFRCNT 0x34
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#define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38
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#define ATAPI_OFFSET_REG_TIM_0 0x40
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#define ATAPI_OFFSET_PIO_TIM_0 0x44
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#define ATAPI_OFFSET_PIO_TIM_1 0x48
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#define ATAPI_OFFSET_MULTI_TIM_0 0x50
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#define ATAPI_OFFSET_MULTI_TIM_1 0x54
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#define ATAPI_OFFSET_MULTI_TIM_2 0x58
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#define ATAPI_OFFSET_ULTRA_TIM_0 0x60
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#define ATAPI_OFFSET_ULTRA_TIM_1 0x64
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#define ATAPI_OFFSET_ULTRA_TIM_2 0x68
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#define ATAPI_OFFSET_ULTRA_TIM_3 0x6c
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#define ATAPI_GET_CONTROL(base)\
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bfin_read16(base + ATAPI_OFFSET_CONTROL)
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#define ATAPI_SET_CONTROL(base, val)\
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bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
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#define ATAPI_GET_STATUS(base)\
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bfin_read16(base + ATAPI_OFFSET_STATUS)
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#define ATAPI_GET_DEV_ADDR(base)\
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bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
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#define ATAPI_SET_DEV_ADDR(base, val)\
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bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
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#define ATAPI_GET_DEV_TXBUF(base)\
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bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
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#define ATAPI_SET_DEV_TXBUF(base, val)\
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bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
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#define ATAPI_GET_DEV_RXBUF(base)\
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bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
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#define ATAPI_SET_DEV_RXBUF(base, val)\
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bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
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#define ATAPI_GET_INT_MASK(base)\
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bfin_read16(base + ATAPI_OFFSET_INT_MASK)
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#define ATAPI_SET_INT_MASK(base, val)\
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bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
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#define ATAPI_GET_INT_STATUS(base)\
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bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
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#define ATAPI_SET_INT_STATUS(base, val)\
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bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
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#define ATAPI_GET_XFER_LEN(base)\
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bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
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#define ATAPI_SET_XFER_LEN(base, val)\
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bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
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#define ATAPI_GET_LINE_STATUS(base)\
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bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
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#define ATAPI_GET_SM_STATE(base)\
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bfin_read16(base + ATAPI_OFFSET_SM_STATE)
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#define ATAPI_GET_TERMINATE(base)\
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bfin_read16(base + ATAPI_OFFSET_TERMINATE)
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#define ATAPI_SET_TERMINATE(base, val)\
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bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
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#define ATAPI_GET_PIO_TFRCNT(base)\
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bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
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#define ATAPI_GET_DMA_TFRCNT(base)\
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bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
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#define ATAPI_GET_UMAIN_TFRCNT(base)\
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bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
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#define ATAPI_GET_UDMAOUT_TFRCNT(base)\
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bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
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#define ATAPI_GET_REG_TIM_0(base)\
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bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
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#define ATAPI_SET_REG_TIM_0(base, val)\
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bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
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#define ATAPI_GET_PIO_TIM_0(base)\
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bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
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#define ATAPI_SET_PIO_TIM_0(base, val)\
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bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
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#define ATAPI_GET_PIO_TIM_1(base)\
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bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
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#define ATAPI_SET_PIO_TIM_1(base, val)\
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bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
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#define ATAPI_GET_MULTI_TIM_0(base)\
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bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
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#define ATAPI_SET_MULTI_TIM_0(base, val)\
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bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
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#define ATAPI_GET_MULTI_TIM_1(base)\
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bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
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#define ATAPI_SET_MULTI_TIM_1(base, val)\
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bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
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#define ATAPI_GET_MULTI_TIM_2(base)\
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bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
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#define ATAPI_SET_MULTI_TIM_2(base, val)\
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bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
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#define ATAPI_GET_ULTRA_TIM_0(base)\
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bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
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#define ATAPI_SET_ULTRA_TIM_0(base, val)\
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bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
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#define ATAPI_GET_ULTRA_TIM_1(base)\
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bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
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#define ATAPI_SET_ULTRA_TIM_1(base, val)\
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bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
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#define ATAPI_GET_ULTRA_TIM_2(base)\
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bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
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#define ATAPI_SET_ULTRA_TIM_2(base, val)\
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bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
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#define ATAPI_GET_ULTRA_TIM_3(base)\
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bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
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#define ATAPI_SET_ULTRA_TIM_3(base, val)\
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bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
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#endif
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