upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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149 lines
3.9 KiB
149 lines
3.9 KiB
/*
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* (C) Copyright 2008-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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/*
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* This code can configure those two Crucial SODIMM's:
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*
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* Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
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* Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
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*
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*/
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#define TEST_ADDR 0x10000000
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#define TEST_MAGIC 0x11223344
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static void wait_init_complete(void)
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{
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u32 val;
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do {
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mfsdram(SDRAM_MCSTAT, val);
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} while (!(val & 0x80000000));
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}
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static void ddr_start(void)
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{
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mtsdram(SDRAM_MCOPT2, 0x28000000);
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wait_init_complete();
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}
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static void ddr_init_common(void)
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{
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/*
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* Reset the DDR-SDRAM controller.
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*/
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mtsdr(SDR0_SRST, (0x80000000 >> 10));
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mtsdr(SDR0_SRST, 0x00000000);
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/*
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* These values are cloned from a running NOR booting
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* Canyonlands with SPD-DDR2 detection and calibration
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* enabled. This will only work for the same memory
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* configuration as used here:
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*
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*/
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mtsdram(SDRAM_MCOPT2, 0x00000000);
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mtsdram(SDRAM_MODT0, 0x01000000);
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mtsdram(SDRAM_WRDTR, 0x82000823);
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mtsdram(SDRAM_CLKTR, 0x40000000);
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mtsdram(SDRAM_MB0CF, 0x00000201);
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mtsdram(SDRAM_RTR, 0x06180000);
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mtsdram(SDRAM_SDTR1, 0x80201000);
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mtsdram(SDRAM_SDTR2, 0x42103243);
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mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
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mtsdram(SDRAM_MMODE, 0x00000632);
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mtsdram(SDRAM_MEMODE, 0x00000040);
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mtsdram(SDRAM_INITPLR0, 0xB5380000);
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mtsdram(SDRAM_INITPLR1, 0x82100400);
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mtsdram(SDRAM_INITPLR2, 0x80820000);
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mtsdram(SDRAM_INITPLR3, 0x80830000);
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mtsdram(SDRAM_INITPLR4, 0x80810040);
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mtsdram(SDRAM_INITPLR5, 0x80800532);
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mtsdram(SDRAM_INITPLR6, 0x82100400);
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mtsdram(SDRAM_INITPLR7, 0x8A080000);
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mtsdram(SDRAM_INITPLR8, 0x8A080000);
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mtsdram(SDRAM_INITPLR9, 0x8A080000);
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mtsdram(SDRAM_INITPLR10, 0x8A080000);
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mtsdram(SDRAM_INITPLR11, 0x80000432);
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mtsdram(SDRAM_INITPLR12, 0x808103C0);
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mtsdram(SDRAM_INITPLR13, 0x80810040);
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mtsdram(SDRAM_INITPLR14, 0x00000000);
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mtsdram(SDRAM_INITPLR15, 0x00000000);
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mtsdram(SDRAM_RDCC, 0x40000000);
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mtsdram(SDRAM_RQDC, 0x80000038);
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mtsdram(SDRAM_RFDC, 0x00000257);
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mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
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mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */
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}
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phys_size_t initdram(int board_type)
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{
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/*
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* First try init for this module:
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*
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* Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
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*/
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ddr_init_common();
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/*
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* Crucial CT6464AC667.8FB - 512MB SO-DIMM
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*/
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mtdcr(SDRAM_R0BAS, 0x0000F800);
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mtdcr(SDRAM_R1BAS, 0x0400F800);
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mtsdram(SDRAM_MCOPT1, 0x05122000);
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mtsdram(SDRAM_CODT, 0x02800021);
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mtsdram(SDRAM_MB1CF, 0x00000201);
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ddr_start();
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/*
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* Now test if the dual-ranked module is really installed
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* by checking an address in the upper 256MByte region
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*/
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out_be32((void *)TEST_ADDR, TEST_MAGIC);
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if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) {
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/*
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* The test failed, so we assume that the single
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* ranked module is installed:
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*
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* Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
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*/
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ddr_init_common();
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mtdcr(SDRAM_R0BAS, 0x0000F000);
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mtsdram(SDRAM_MCOPT1, 0x05322000);
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mtsdram(SDRAM_CODT, 0x00800021);
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ddr_start();
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}
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return CONFIG_SYS_MBYTES_SDRAM << 20;
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}
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