upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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809 lines
19 KiB
809 lines
19 KiB
/*
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* INCA-IP internal switch ethernet driver.
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*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/inca-ip.h>
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#include <asm/addrspace.h>
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#define NUM_RX_DESC PKTBUFSRX
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#define NUM_TX_DESC 3
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#define TOUT_LOOP 1000000
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#define DELAY udelay(10000)
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/* Sometimes the store word instruction hangs while writing to one
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* of the Switch registers. Moving the instruction into a separate
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* function somehow makes the problem go away.
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*/
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static void SWORD(volatile u32 * reg, u32 value)
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{
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*reg = value;
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}
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#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
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#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
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#define SW_WRITE_REG(reg, value) \
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SWORD(reg, value);\
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DELAY;\
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SWORD(reg, value);
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#define SW_READ_REG(reg, value) \
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value = (u32)*((volatile u32*)reg);\
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DELAY;\
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value = (u32)*((volatile u32*)reg);
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#define INCA_DMA_TX_POLLING_TIME 0x07
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#define INCA_DMA_RX_POLLING_TIME 0x07
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#define INCA_DMA_TX_HOLD 0x80000000
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#define INCA_DMA_TX_EOP 0x40000000
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#define INCA_DMA_TX_SOP 0x20000000
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#define INCA_DMA_TX_ICPT 0x10000000
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#define INCA_DMA_TX_IEOP 0x08000000
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#define INCA_DMA_RX_C 0x80000000
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#define INCA_DMA_RX_SOP 0x40000000
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#define INCA_DMA_RX_EOP 0x20000000
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#define INCA_SWITCH_PHY_SPEED_10H 0x1
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#define INCA_SWITCH_PHY_SPEED_10F 0x5
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#define INCA_SWITCH_PHY_SPEED_100H 0x2
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#define INCA_SWITCH_PHY_SPEED_100F 0x6
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/************************ Auto MDIX settings ************************/
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#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
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#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
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#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
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#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
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#define WAIT_SIGNAL_RETRIES 100
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#define WAIT_LINK_RETRIES 100
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#define LINK_RETRY_DELAY 2000 /* ms */
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/********************************************************************/
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typedef struct
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{
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union {
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struct {
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volatile u32 HOLD :1;
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volatile u32 ICpt :1;
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volatile u32 IEop :1;
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volatile u32 offset :3;
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volatile u32 reserved0 :4;
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volatile u32 NFB :22;
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}field;
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volatile u32 word;
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}params;
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volatile u32 nextRxDescPtr;
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volatile u32 RxDataPtr;
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union {
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struct {
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volatile u32 C :1;
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volatile u32 Sop :1;
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volatile u32 Eop :1;
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volatile u32 reserved3 :12;
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volatile u32 NBT :17;
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}field;
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volatile u32 word;
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}status;
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} inca_rx_descriptor_t;
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typedef struct
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{
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union {
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struct {
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volatile u32 HOLD :1;
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volatile u32 Eop :1;
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volatile u32 Sop :1;
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volatile u32 ICpt :1;
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volatile u32 IEop :1;
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volatile u32 reserved0 :5;
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volatile u32 NBA :22;
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}field;
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volatile u32 word;
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}params;
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volatile u32 nextTxDescPtr;
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volatile u32 TxDataPtr;
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volatile u32 C :1;
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volatile u32 reserved3 :31;
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} inca_tx_descriptor_t;
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static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
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static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
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static int tx_new, rx_new, tx_hold, rx_hold;
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static int tx_old_hold = -1;
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static int initialized = 0;
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static int inca_switch_init(struct eth_device *dev, bd_t * bis);
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static int inca_switch_send(struct eth_device *dev, void *packet, int length);
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static int inca_switch_recv(struct eth_device *dev);
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static void inca_switch_halt(struct eth_device *dev);
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static void inca_init_switch_chip(void);
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static void inca_dma_init(void);
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static int inca_amdix(void);
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int inca_switch_initialize(bd_t * bis)
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{
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struct eth_device *dev;
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#if 0
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printf("Entered inca_switch_initialize()\n");
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#endif
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if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
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printf("Failed to allocate memory\n");
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return 0;
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}
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memset(dev, 0, sizeof(*dev));
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inca_dma_init();
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inca_init_switch_chip();
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#if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
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inca_amdix();
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#endif
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sprintf(dev->name, "INCA-IP Switch");
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dev->init = inca_switch_init;
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dev->halt = inca_switch_halt;
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dev->send = inca_switch_send;
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dev->recv = inca_switch_recv;
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eth_register(dev);
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#if 0
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printf("Leaving inca_switch_initialize()\n");
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#endif
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return 0;
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}
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static int inca_switch_init(struct eth_device *dev, bd_t * bis)
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{
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int i;
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u32 v, regValue;
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u16 wTmp;
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#if 0
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printf("Entering inca_switch_init()\n");
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#endif
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/* Set MAC address.
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*/
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wTmp = (u16)dev->enetaddr[0];
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regValue = (wTmp << 8) | dev->enetaddr[1];
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SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
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wTmp = (u16)dev->enetaddr[2];
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regValue = (wTmp << 8) | dev->enetaddr[3];
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regValue = regValue << 16;
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wTmp = (u16)dev->enetaddr[4];
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regValue |= (wTmp<<8) | dev->enetaddr[5];
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SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
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/* Initialize the descriptor rings.
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*/
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for (i = 0; i < NUM_RX_DESC; i++) {
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inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
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memset(rx_desc, 0, sizeof(rx_ring[i]));
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/* Set maximum size of receive buffer.
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*/
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rx_desc->params.field.NFB = PKTSIZE_ALIGN;
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/* Set the offset of the receive buffer. Zero means
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* that the offset mechanism is not used.
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*/
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rx_desc->params.field.offset = 0;
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/* Check if it is the last descriptor.
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*/
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if (i == (NUM_RX_DESC - 1)) {
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/* Let the last descriptor point to the first
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* one.
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*/
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rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
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} else {
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/* Set the address of the next descriptor.
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*/
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rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
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}
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rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
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}
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#if 0
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printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
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printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
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#endif
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for (i = 0; i < NUM_TX_DESC; i++) {
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inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
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memset(tx_desc, 0, sizeof(tx_ring[i]));
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tx_desc->params.word = 0;
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tx_desc->params.field.HOLD = 1;
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tx_desc->C = 1;
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/* Check if it is the last descriptor.
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*/
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if (i == (NUM_TX_DESC - 1)) {
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/* Let the last descriptor point to the
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* first one.
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*/
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tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
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} else {
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/* Set the address of the next descriptor.
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*/
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tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
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}
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}
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/* Initialize RxDMA.
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*/
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DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
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debug("RX status = 0x%08X\n", v);
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/* Writing to the FRDA of CHANNEL.
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*/
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DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
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/* Writing to the COMMAND REG.
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*/
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DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
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/* Initialize TxDMA.
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*/
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DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
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debug("TX status = 0x%08X\n", v);
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/* Writing to the FRDA of CHANNEL.
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*/
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DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
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tx_new = rx_new = 0;
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tx_hold = NUM_TX_DESC - 1;
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rx_hold = NUM_RX_DESC - 1;
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#if 0
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rx_ring[rx_hold].params.field.HOLD = 1;
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#endif
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/* enable spanning tree forwarding, enable the CPU port */
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/* ST_PT:
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* CPS (CPU port status) 0x3 (forwarding)
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* LPS (LAN port status) 0x3 (forwarding)
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* PPS (PC port status) 0x3 (forwarding)
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*/
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SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
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#if 0
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printf("Leaving inca_switch_init()\n");
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#endif
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return 0;
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}
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static int inca_switch_send(struct eth_device *dev, void *packet, int length)
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{
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int i;
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int res = -1;
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u32 command;
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u32 regValue;
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inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
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#if 0
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printf("Entered inca_switch_send()\n");
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#endif
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if (length <= 0) {
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printf ("%s: bad packet size: %d\n", dev->name, length);
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goto Done;
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}
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for(i = 0; tx_desc->C == 0; i++) {
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if (i >= TOUT_LOOP) {
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printf("%s: tx error buffer not ready\n", dev->name);
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goto Done;
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}
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}
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if (tx_old_hold >= 0) {
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((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
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}
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tx_old_hold = tx_hold;
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tx_desc->params.word =
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(INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
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tx_desc->C = 0;
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tx_desc->TxDataPtr = (u32)packet;
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tx_desc->params.field.NBA = length;
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((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
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tx_hold = tx_new;
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tx_new = (tx_new + 1) % NUM_TX_DESC;
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if (! initialized) {
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command = INCA_IP_DMA_DMA_TXCCR0_INIT;
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initialized = 1;
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} else {
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command = INCA_IP_DMA_DMA_TXCCR0_HR;
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}
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DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
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regValue |= command;
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#if 0
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printf("regValue = 0x%x\n", regValue);
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#endif
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DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
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#if 1
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for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
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if (i >= TOUT_LOOP) {
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printf("%s: tx buffer not ready\n", dev->name);
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goto Done;
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}
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}
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#endif
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res = length;
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Done:
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#if 0
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printf("Leaving inca_switch_send()\n");
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#endif
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return res;
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}
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static int inca_switch_recv(struct eth_device *dev)
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{
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int length = 0;
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inca_rx_descriptor_t * rx_desc;
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#if 0
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printf("Entered inca_switch_recv()\n");
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#endif
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for (;;) {
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rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
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if (rx_desc->status.field.C == 0) {
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break;
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}
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#if 0
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rx_ring[rx_new].params.field.HOLD = 1;
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#endif
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if (! rx_desc->status.field.Eop) {
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printf("Partly received packet!!!\n");
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break;
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}
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length = rx_desc->status.field.NBT;
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rx_desc->status.word &=
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~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
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#if 0
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{
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int i;
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for (i=0;i<length - 4;i++) {
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if (i % 16 == 0) printf("\n%04x: ", i);
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printf("%02X ", NetRxPackets[rx_new][i]);
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}
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printf("\n");
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}
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#endif
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if (length) {
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#if 0
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printf("Received %d bytes\n", length);
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#endif
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NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
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} else {
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#if 1
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printf("Zero length!!!\n");
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#endif
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}
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((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
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rx_hold = rx_new;
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rx_new = (rx_new + 1) % NUM_RX_DESC;
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}
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#if 0
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printf("Leaving inca_switch_recv()\n");
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#endif
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return length;
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}
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static void inca_switch_halt(struct eth_device *dev)
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{
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#if 0
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printf("Entered inca_switch_halt()\n");
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#endif
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#if 1
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initialized = 0;
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#endif
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#if 1
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/* Disable forwarding to the CPU port.
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*/
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SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
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/* Close RxDMA channel.
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*/
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DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
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/* Close TxDMA channel.
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*/
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DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
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#endif
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#if 0
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printf("Leaving inca_switch_halt()\n");
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#endif
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}
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static void inca_init_switch_chip(void)
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{
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u32 regValue;
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/* To workaround a problem with collision counter
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* (see Errata sheet).
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*/
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SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
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SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
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#if 1
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/* init MDIO configuration:
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* MDS (Poll speed): 0x01 (4ms)
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* PHY_LAN_ADDR: 0x06
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* PHY_PC_ADDR: 0x05
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* UEP (Use External PHY): 0x00 (Internal PHY is used)
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* PS (Port Select): 0x00 (PT/UMM for LAN)
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* PT (PHY Test): 0x00 (no test mode)
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* UMM (Use MDIO Mode): 0x00 (state machine is disabled)
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*/
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SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
|
|
|
|
/* init PHY:
|
|
* SL (Auto Neg. Speed for LAN)
|
|
* SP (Auto Neg. Speed for PC)
|
|
* LL (Link Status for LAN)
|
|
* LP (Link Status for PC)
|
|
* DL (Duplex Status for LAN)
|
|
* DP (Duplex Status for PC)
|
|
* PL (Auto Neg. Pause Status for LAN)
|
|
* PP (Auto Neg. Pause Status for PC)
|
|
*/
|
|
SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
|
|
|
|
/* MDIO_ACC:
|
|
* RA (Request/Ack) 0x01 (Request)
|
|
* RW (Read/Write) 0x01 (Write)
|
|
* PHY_ADDR 0x05 (PC)
|
|
* REG_ADDR 0x00 (PHY_BCR: basic control register)
|
|
* PHY_DATA 0x8000
|
|
* Reset - software reset
|
|
* LB (loop back) - normal
|
|
* SS (speed select) - 10 Mbit/s
|
|
* ANE (auto neg. enable) - enable
|
|
* PD (power down) - normal
|
|
* ISO (isolate) - normal
|
|
* RAN (restart auto neg.) - normal
|
|
* DM (duplex mode) - half duplex
|
|
* CT (collision test) - enable
|
|
*/
|
|
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
|
|
|
|
/* MDIO_ACC:
|
|
* RA (Request/Ack) 0x01 (Request)
|
|
* RW (Read/Write) 0x01 (Write)
|
|
* PHY_ADDR 0x06 (LAN)
|
|
* REG_ADDR 0x00 (PHY_BCR: basic control register)
|
|
* PHY_DATA 0x8000
|
|
* Reset - software reset
|
|
* LB (loop back) - normal
|
|
* SS (speed select) - 10 Mbit/s
|
|
* ANE (auto neg. enable) - enable
|
|
* PD (power down) - normal
|
|
* ISO (isolate) - normal
|
|
* RAN (restart auto neg.) - normal
|
|
* DM (duplex mode) - half duplex
|
|
* CT (collision test) - enable
|
|
*/
|
|
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
|
|
|
|
#endif
|
|
|
|
/* Make sure the CPU port is disabled for now. We
|
|
* don't want packets to get stacked for us until
|
|
* we enable DMA and are prepared to receive them.
|
|
*/
|
|
SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
|
|
|
|
SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
|
|
|
|
/* CRC GEN is enabled.
|
|
*/
|
|
regValue |= 0x00000200;
|
|
SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
|
|
|
|
/* ADD TAG is disabled.
|
|
*/
|
|
SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
|
|
regValue &= ~0x00000002;
|
|
SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
|
|
}
|
|
|
|
|
|
static void inca_dma_init(void)
|
|
{
|
|
/* Switch off all DMA channels.
|
|
*/
|
|
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
|
|
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
|
|
|
|
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
|
|
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
|
|
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
|
|
|
|
/* Setup TX channel polling time.
|
|
*/
|
|
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
|
|
|
|
/* Setup RX channel polling time.
|
|
*/
|
|
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
|
|
|
|
/* ERRATA: write reset value into the DMA RX IMR register.
|
|
*/
|
|
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
|
|
|
|
/* Just in case: disable all transmit interrupts also.
|
|
*/
|
|
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
|
|
|
|
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
|
|
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
|
|
}
|
|
|
|
#if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
|
|
static int inca_amdix(void)
|
|
{
|
|
u32 phyReg1 = 0;
|
|
u32 phyReg4 = 0;
|
|
u32 phyReg5 = 0;
|
|
u32 phyReg6 = 0;
|
|
u32 phyReg31 = 0;
|
|
u32 regEphy = 0;
|
|
int mdi_flag;
|
|
int retries;
|
|
|
|
/* Setup GPIO pins.
|
|
*/
|
|
*INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
|
|
*INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
|
|
|
|
#if 0
|
|
/* Wait for signal.
|
|
*/
|
|
retries = WAIT_SIGNAL_RETRIES;
|
|
while (--retries) {
|
|
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
|
(0x1 << 31) | /* RA */
|
|
(0x0 << 30) | /* Read */
|
|
(0x6 << 21) | /* LAN */
|
|
(17 << 16)); /* PHY_MCSR */
|
|
do {
|
|
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
|
|
} while (phyReg1 & (1 << 31));
|
|
|
|
if (phyReg1 & (1 << 1)) {
|
|
/* Signal detected */
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!retries)
|
|
goto Fail;
|
|
#endif
|
|
|
|
/* Set MDI mode.
|
|
*/
|
|
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
|
|
mdi_flag = 1;
|
|
|
|
/* Wait for link.
|
|
*/
|
|
retries = WAIT_LINK_RETRIES;
|
|
while (--retries) {
|
|
udelay(LINK_RETRY_DELAY * 1000);
|
|
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
|
(0x1 << 31) | /* RA */
|
|
(0x0 << 30) | /* Read */
|
|
(0x6 << 21) | /* LAN */
|
|
(1 << 16)); /* PHY_BSR */
|
|
do {
|
|
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
|
|
} while (phyReg1 & (1 << 31));
|
|
|
|
if (phyReg1 & (1 << 2)) {
|
|
/* Link is up */
|
|
break;
|
|
} else if (mdi_flag) {
|
|
/* Set MDIX mode */
|
|
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
|
|
mdi_flag = 0;
|
|
} else {
|
|
/* Set MDI mode */
|
|
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
|
|
mdi_flag = 1;
|
|
}
|
|
}
|
|
|
|
if (!retries) {
|
|
goto Fail;
|
|
} else {
|
|
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
|
(0x1 << 31) | /* RA */
|
|
(0x0 << 30) | /* Read */
|
|
(0x6 << 21) | /* LAN */
|
|
(1 << 16)); /* PHY_BSR */
|
|
do {
|
|
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
|
|
} while (phyReg1 & (1 << 31));
|
|
|
|
/* Auto-negotiation / Parallel detection complete
|
|
*/
|
|
if (phyReg1 & (1 << 5)) {
|
|
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
|
(0x1 << 31) | /* RA */
|
|
(0x0 << 30) | /* Read */
|
|
(0x6 << 21) | /* LAN */
|
|
(31 << 16)); /* PHY_SCSR */
|
|
do {
|
|
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
|
|
} while (phyReg31 & (1 << 31));
|
|
|
|
switch ((phyReg31 >> 2) & 0x7) {
|
|
case INCA_SWITCH_PHY_SPEED_10H:
|
|
/* 10Base-T Half-duplex */
|
|
regEphy = 0;
|
|
break;
|
|
case INCA_SWITCH_PHY_SPEED_10F:
|
|
/* 10Base-T Full-duplex */
|
|
regEphy = INCA_IP_Switch_EPHY_DL;
|
|
break;
|
|
case INCA_SWITCH_PHY_SPEED_100H:
|
|
/* 100Base-TX Half-duplex */
|
|
regEphy = INCA_IP_Switch_EPHY_SL;
|
|
break;
|
|
case INCA_SWITCH_PHY_SPEED_100F:
|
|
/* 100Base-TX Full-duplex */
|
|
regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL;
|
|
break;
|
|
}
|
|
|
|
/* In case of Auto-negotiation,
|
|
* update the negotiated PAUSE support status
|
|
*/
|
|
if (phyReg1 & (1 << 3)) {
|
|
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
|
(0x1 << 31) | /* RA */
|
|
(0x0 << 30) | /* Read */
|
|
(0x6 << 21) | /* LAN */
|
|
(6 << 16)); /* MII_EXPANSION */
|
|
do {
|
|
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
|
|
} while (phyReg6 & (1 << 31));
|
|
|
|
/* We are Autoneg-able.
|
|
* Is Link partner also able to autoneg?
|
|
*/
|
|
if (phyReg6 & (1 << 0)) {
|
|
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
|
(0x1 << 31) | /* RA */
|
|
(0x0 << 30) | /* Read */
|
|
(0x6 << 21) | /* LAN */
|
|
(4 << 16)); /* MII_ADVERTISE */
|
|
do {
|
|
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
|
|
} while (phyReg4 & (1 << 31));
|
|
|
|
/* We advertise PAUSE capab.
|
|
* Does link partner also advertise it?
|
|
*/
|
|
if (phyReg4 & (1 << 10)) {
|
|
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
|
(0x1 << 31) | /* RA */
|
|
(0x0 << 30) | /* Read */
|
|
(0x6 << 21) | /* LAN */
|
|
(5 << 16)); /* MII_LPA */
|
|
do {
|
|
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
|
|
} while (phyReg5 & (1 << 31));
|
|
|
|
/* Link partner is PAUSE capab.
|
|
*/
|
|
if (phyReg5 & (1 << 10)) {
|
|
regEphy |= INCA_IP_Switch_EPHY_PL;
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
/* Link is up */
|
|
regEphy |= INCA_IP_Switch_EPHY_LL;
|
|
|
|
SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
Fail:
|
|
printf("No Link on LAN port\n");
|
|
return -1;
|
|
}
|
|
#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */
|
|
|