upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
739 lines
20 KiB
739 lines
20 KiB
/*
|
|
* Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
|
|
*
|
|
* Dave Liu <daveliu@freescale.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef __CONFIG_H
|
|
#define __CONFIG_H
|
|
|
|
/*
|
|
* High Level Configuration Options
|
|
*/
|
|
#define CONFIG_E300 1 /* E300 family */
|
|
#define CONFIG_QE 1 /* Has QE */
|
|
#define CONFIG_MPC83xx 1 /* MPC83xx family */
|
|
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
|
|
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
|
|
|
|
#define CONFIG_SYS_TEXT_BASE 0xFE000000
|
|
|
|
#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
|
|
#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
|
|
|
|
/*
|
|
* System Clock Setup
|
|
*/
|
|
#ifdef CONFIG_CLKIN_33MHZ
|
|
#ifdef CONFIG_PCISLAVE
|
|
#define CONFIG_83XX_PCICLK 33330000 /* in HZ */
|
|
#else
|
|
#define CONFIG_83XX_CLKIN 33330000 /* in Hz */
|
|
#endif
|
|
|
|
#ifndef CONFIG_SYS_CLK_FREQ
|
|
#define CONFIG_SYS_CLK_FREQ 33330000
|
|
#endif
|
|
|
|
#elif defined(CONFIG_CLKIN_66MHZ)
|
|
#ifdef CONFIG_PCISLAVE
|
|
#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
|
|
#else
|
|
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
|
|
#endif
|
|
|
|
#ifndef CONFIG_SYS_CLK_FREQ
|
|
#define CONFIG_SYS_CLK_FREQ 66000000
|
|
#endif
|
|
#else
|
|
#error Unknown oscillator frequency.
|
|
#endif
|
|
|
|
/*
|
|
* Hardware Reset Configuration Word
|
|
*/
|
|
#ifdef CONFIG_CLKIN_33MHZ
|
|
#define CONFIG_SYS_HRCW_LOW (\
|
|
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
|
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
|
HRCWL_CSB_TO_CLKIN_8X1 |\
|
|
HRCWL_VCO_1X2 |\
|
|
HRCWL_CE_PLL_VCO_DIV_4 |\
|
|
HRCWL_CE_PLL_DIV_1X1 |\
|
|
HRCWL_CE_TO_PLL_1X15 |\
|
|
HRCWL_CORE_TO_CSB_2X1)
|
|
#elif defined(CONFIG_CLKIN_66MHZ)
|
|
#define CONFIG_SYS_HRCW_LOW (\
|
|
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
|
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
|
HRCWL_CSB_TO_CLKIN_4X1 |\
|
|
HRCWL_VCO_1X2 |\
|
|
HRCWL_CE_PLL_VCO_DIV_4 |\
|
|
HRCWL_CE_PLL_DIV_1X1 |\
|
|
HRCWL_CE_TO_PLL_1X6 |\
|
|
HRCWL_CORE_TO_CSB_2X1)
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCISLAVE
|
|
#define CONFIG_SYS_HRCW_HIGH (\
|
|
HRCWH_PCI_AGENT |\
|
|
HRCWH_PCI1_ARBITER_DISABLE |\
|
|
HRCWH_PCICKDRV_DISABLE |\
|
|
HRCWH_CORE_ENABLE |\
|
|
HRCWH_FROM_0XFFF00100 |\
|
|
HRCWH_BOOTSEQ_DISABLE |\
|
|
HRCWH_SW_WATCHDOG_DISABLE |\
|
|
HRCWH_ROM_LOC_LOCAL_16BIT)
|
|
#else
|
|
#define CONFIG_SYS_HRCW_HIGH (\
|
|
HRCWH_PCI_HOST |\
|
|
HRCWH_PCI1_ARBITER_ENABLE |\
|
|
HRCWH_PCICKDRV_ENABLE |\
|
|
HRCWH_CORE_ENABLE |\
|
|
HRCWH_FROM_0X00000100 |\
|
|
HRCWH_BOOTSEQ_DISABLE |\
|
|
HRCWH_SW_WATCHDOG_DISABLE |\
|
|
HRCWH_ROM_LOC_LOCAL_16BIT)
|
|
#endif
|
|
|
|
/*
|
|
* System IO Config
|
|
*/
|
|
#define CONFIG_SYS_SICRH 0x00000000
|
|
#define CONFIG_SYS_SICRL 0x40000000
|
|
|
|
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
|
|
#define CONFIG_BOARD_EARLY_INIT_R
|
|
|
|
/*
|
|
* IMMR new address
|
|
*/
|
|
#define CONFIG_SYS_IMMR 0xE0000000
|
|
|
|
/*
|
|
* DDR Setup
|
|
*/
|
|
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
|
|
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
|
/* + 256M */
|
|
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000)
|
|
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
|
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
|
|
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
|
|
|
#define CONFIG_SYS_83XX_DDR_USES_CS0
|
|
|
|
#define CONFIG_DDR_ECC /* support DDR ECC function */
|
|
#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
|
|
|
|
/*
|
|
* DDRCDR - DDR Control Driver Register
|
|
*/
|
|
#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
|
|
|
|
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
|
#if defined(CONFIG_SPD_EEPROM)
|
|
/*
|
|
* Determine DDR configuration from I2C interface.
|
|
*/
|
|
#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
|
|
#else
|
|
/*
|
|
* Manually set up DDR parameters
|
|
*/
|
|
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
|
|
#if defined(CONFIG_DDR_II)
|
|
#define CONFIG_SYS_DDRCDR 0x80080001
|
|
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
|
|
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
|
|
#define CONFIG_SYS_DDR_TIMING_0 0x00220802
|
|
#define CONFIG_SYS_DDR_TIMING_1 0x38357322
|
|
#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
|
|
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
|
#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
|
|
#define CONFIG_SYS_DDR_MODE 0x47d00432
|
|
#define CONFIG_SYS_DDR_MODE2 0x8000c000
|
|
#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
|
|
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
|
|
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
|
#else
|
|
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
|
|
| CSCONFIG_ROW_BIT_13 \
|
|
| CSCONFIG_COL_BIT_9)
|
|
#define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG
|
|
#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
|
|
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
|
|
#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
|
|
#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
|
|
#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
|
|
#endif
|
|
#endif
|
|
|
|
/*
|
|
* Memory test
|
|
*/
|
|
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
|
|
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
|
|
#define CONFIG_SYS_MEMTEST_END 0x00100000
|
|
|
|
/*
|
|
* The reserved memory
|
|
*/
|
|
|
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
|
|
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
|
#define CONFIG_SYS_RAMBOOT
|
|
#else
|
|
#undef CONFIG_SYS_RAMBOOT
|
|
#endif
|
|
|
|
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
|
|
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
|
|
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
|
|
|
|
/*
|
|
* Initial RAM Base Address Setup
|
|
*/
|
|
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
|
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
|
|
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
|
|
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
|
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
|
|
/*
|
|
* Local Bus Configuration & Clock Setup
|
|
*/
|
|
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
|
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
|
|
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
|
|
|
/*
|
|
* FLASH on the Local Bus
|
|
*/
|
|
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
|
|
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
|
|
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
|
|
#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
|
|
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
|
|
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
|
|
|
/* Window base at flash base */
|
|
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
|
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
|
|
|
|
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
|
|
| BR_PS_16 /* 16 bit port */ \
|
|
| BR_MS_GPCM /* MSEL = GPCM */ \
|
|
| BR_V) /* valid */
|
|
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
|
|
| OR_GPCM_XAM \
|
|
| OR_GPCM_CSNT \
|
|
| OR_GPCM_ACS_DIV2 \
|
|
| OR_GPCM_XACS \
|
|
| OR_GPCM_SCY_15 \
|
|
| OR_GPCM_TRLX_SET \
|
|
| OR_GPCM_EHTR_SET \
|
|
| OR_GPCM_EAD)
|
|
|
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
|
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
|
|
|
|
#undef CONFIG_SYS_FLASH_CHECKSUM
|
|
|
|
/*
|
|
* BCSR on the Local Bus
|
|
*/
|
|
#define CONFIG_SYS_BCSR 0xF8000000
|
|
/* Access window base at BCSR base */
|
|
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
|
|
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
|
|
|
|
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
|
|
| BR_PS_8 \
|
|
| BR_MS_GPCM \
|
|
| BR_V)
|
|
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
|
|
| OR_GPCM_XAM \
|
|
| OR_GPCM_CSNT \
|
|
| OR_GPCM_XACS \
|
|
| OR_GPCM_SCY_15 \
|
|
| OR_GPCM_TRLX_SET \
|
|
| OR_GPCM_EHTR_SET \
|
|
| OR_GPCM_EAD)
|
|
/* 0xFFFFE9F7 */
|
|
|
|
/*
|
|
* SDRAM on the Local Bus
|
|
*/
|
|
#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
|
|
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
|
|
|
|
#define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */
|
|
|
|
#ifdef CONFIG_SYS_LB_SDRAM
|
|
#define CONFIG_SYS_LBLAWBAR2 0
|
|
#define CONFIG_SYS_LBLAWAR2 (LBLAWAR_EN | LBLAWAR_64MB)
|
|
|
|
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
|
|
/*
|
|
* Base Register 2 and Option Register 2 configure SDRAM.
|
|
*
|
|
* For BR2, need:
|
|
* Base address = BR[0:16] = dynamic
|
|
* port size = 32-bits = BR2[19:20] = 11
|
|
* no parity checking = BR2[21:22] = 00
|
|
* SDRAM for MSEL = BR2[24:26] = 011
|
|
* Valid = BR[31] = 1
|
|
*
|
|
* 0 4 8 12 16 20 24 28
|
|
* xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
|
|
*/
|
|
|
|
/* Port size=32bit, MSEL=DRAM */
|
|
#define CONFIG_SYS_BR2 (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */
|
|
|
|
/*
|
|
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
|
|
*
|
|
* For OR2, need:
|
|
* 64MB mask for AM, OR2[0:7] = 1111 1100
|
|
* XAM, OR2[17:18] = 11
|
|
* 9 columns OR2[19-21] = 010
|
|
* 13 rows OR2[23-25] = 100
|
|
* EAD set for extra time OR[31] = 1
|
|
*
|
|
* 0 4 8 12 16 20 24 28
|
|
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
|
|
*/
|
|
|
|
#define CONFIG_SYS_OR2 (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
|
|
| OR_SDRAM_XAM \
|
|
| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
|
|
| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
|
|
| OR_SDRAM_EAD)
|
|
/* 0xFC006901 */
|
|
|
|
/* LB sdram refresh timer, about 6us */
|
|
#define CONFIG_SYS_LBC_LSRT 0x32000000
|
|
/* LB refresh timer prescal, 266MHz/32 */
|
|
#define CONFIG_SYS_LBC_MRTPR 0x20000000
|
|
|
|
#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
|
|
|
|
/*
|
|
* SDRAM Controller configuration sequence.
|
|
*/
|
|
#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
|
|
#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
|
|
#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
|
|
#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
|
|
#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
|
|
|
|
#endif
|
|
|
|
/*
|
|
* Windows to access Platform I/O Boards (PIB) via local bus
|
|
*/
|
|
#define CONFIG_SYS_PIB_BASE 0xF8008000
|
|
#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
|
|
|
|
/* [RFC] This LBLAW only covers the 2nd window (CS5) */
|
|
#define CONFIG_SYS_LBLAWBAR3_PRELIM \
|
|
CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE
|
|
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
|
|
|
|
/*
|
|
* CS4 on Local Bus, to PIB
|
|
*/
|
|
/* CS4 base address at 0xf8008000 */
|
|
#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \
|
|
| BR_PS_8 \
|
|
| BR_MS_GPCM \
|
|
| BR_V)
|
|
/* 0xF8008801 */
|
|
#define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \
|
|
| OR_GPCM_XAM \
|
|
| OR_GPCM_CSNT \
|
|
| OR_GPCM_XACS \
|
|
| OR_GPCM_SCY_15 \
|
|
| OR_GPCM_TRLX_SET \
|
|
| OR_GPCM_EHTR_SET \
|
|
| OR_GPCM_EAD)
|
|
/* 0xffffe9f7 */
|
|
|
|
/*
|
|
* CS5 on Local Bus, to PIB
|
|
*/
|
|
/* CS5 base address at 0xf8010000 */
|
|
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + \
|
|
CONFIG_SYS_PIB_WINDOW_SIZE) \
|
|
| BR_PS_8 \
|
|
| BR_MS_GPCM \
|
|
| BR_V)
|
|
/* 0xF8010801 */
|
|
#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \
|
|
| OR_GPCM_XAM \
|
|
| OR_GPCM_CSNT \
|
|
| OR_GPCM_XACS \
|
|
| OR_GPCM_SCY_15 \
|
|
| OR_GPCM_TRLX_SET \
|
|
| OR_GPCM_EHTR_SET \
|
|
| OR_GPCM_EAD)
|
|
/* 0xffffe9f7 */
|
|
|
|
/*
|
|
* Serial Port
|
|
*/
|
|
#define CONFIG_CONS_INDEX 1
|
|
#define CONFIG_SYS_NS16550
|
|
#define CONFIG_SYS_NS16550_SERIAL
|
|
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
|
|
|
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
|
|
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
|
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
|
|
|
|
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
|
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
|
/* Use the HUSH parser */
|
|
#define CONFIG_SYS_HUSH_PARSER
|
|
|
|
/* pass open firmware flat tree */
|
|
#define CONFIG_OF_LIBFDT 1
|
|
#define CONFIG_OF_BOARD_SETUP 1
|
|
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
|
|
|
/* I2C */
|
|
#define CONFIG_SYS_I2C
|
|
#define CONFIG_SYS_I2C_FSL
|
|
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
|
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
|
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
|
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
|
|
|
|
/*
|
|
* Config on-board RTC
|
|
*/
|
|
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
|
|
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
|
|
|
/*
|
|
* General PCI
|
|
* Addresses are mapped 1-1.
|
|
*/
|
|
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
|
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
|
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
|
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
|
|
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
|
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
|
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
|
|
#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
|
|
#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
|
|
|
|
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
|
|
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
|
|
#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
|
|
|
|
|
|
#ifdef CONFIG_PCI
|
|
#define CONFIG_PCI_INDIRECT_BRIDGE
|
|
|
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
|
#define CONFIG_83XX_PCI_STREAMING
|
|
|
|
#undef CONFIG_EEPRO100
|
|
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
|
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
|
|
#define CONFIG_HWCONFIG 1
|
|
|
|
/*
|
|
* QE UEC ethernet configuration
|
|
*/
|
|
#define CONFIG_UEC_ETH
|
|
#define CONFIG_ETHPRIME "UEC0"
|
|
#define CONFIG_PHY_MODE_NEED_CHANGE
|
|
|
|
#define CONFIG_UEC_ETH1 /* GETH1 */
|
|
|
|
#ifdef CONFIG_UEC_ETH1
|
|
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
|
|
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
|
|
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
|
|
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
|
|
#define CONFIG_SYS_UEC1_PHY_ADDR 0
|
|
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
|
|
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
|
|
#endif
|
|
|
|
#define CONFIG_UEC_ETH2 /* GETH2 */
|
|
|
|
#ifdef CONFIG_UEC_ETH2
|
|
#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
|
|
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
|
|
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
|
|
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
|
|
#define CONFIG_SYS_UEC2_PHY_ADDR 1
|
|
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
|
|
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
|
|
#endif
|
|
|
|
/*
|
|
* Environment
|
|
*/
|
|
|
|
#ifndef CONFIG_SYS_RAMBOOT
|
|
#define CONFIG_ENV_IS_IN_FLASH 1
|
|
#define CONFIG_ENV_ADDR \
|
|
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
|
#define CONFIG_ENV_SECT_SIZE 0x20000
|
|
#define CONFIG_ENV_SIZE 0x2000
|
|
#else
|
|
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
|
|
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
|
#define CONFIG_ENV_SIZE 0x2000
|
|
#endif
|
|
|
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
|
|
/*
|
|
* BOOTP options
|
|
*/
|
|
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
#define CONFIG_BOOTP_BOOTPATH
|
|
#define CONFIG_BOOTP_GATEWAY
|
|
#define CONFIG_BOOTP_HOSTNAME
|
|
|
|
|
|
/*
|
|
* Command line configuration.
|
|
*/
|
|
#include <config_cmd_default.h>
|
|
|
|
#define CONFIG_CMD_PING
|
|
#define CONFIG_CMD_I2C
|
|
#define CONFIG_CMD_ASKENV
|
|
#define CONFIG_CMD_SDRAM
|
|
|
|
#if defined(CONFIG_PCI)
|
|
#define CONFIG_CMD_PCI
|
|
#endif
|
|
|
|
#if defined(CONFIG_SYS_RAMBOOT)
|
|
#undef CONFIG_CMD_SAVEENV
|
|
#undef CONFIG_CMD_LOADS
|
|
#endif
|
|
|
|
|
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
|
|
/*
|
|
* Miscellaneous configurable options
|
|
*/
|
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
#else
|
|
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
|
#endif
|
|
|
|
/* Print Buffer Size */
|
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
|
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
|
/* Boot Argument Buffer Size */
|
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
|
|
|
/*
|
|
* For booting Linux, the board info and command line data
|
|
* have to be in the first 256 MB of memory, since this is
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
*/
|
|
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
|
|
|
|
/*
|
|
* Core HID Setup
|
|
*/
|
|
#define CONFIG_SYS_HID0_INIT 0x000000000
|
|
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
|
|
HID0_ENABLE_INSTRUCTION_CACHE)
|
|
#define CONFIG_SYS_HID2 HID2_HBE
|
|
|
|
/*
|
|
* MMU Setup
|
|
*/
|
|
|
|
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
|
#define CONFIG_BAT_RW
|
|
|
|
/* DDR/LBC SDRAM: cacheable */
|
|
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
|
|
| BATL_PP_RW \
|
|
| BATL_MEMCOHERENCE)
|
|
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
|
|
| BATU_BL_256M \
|
|
| BATU_VS \
|
|
| BATU_VP)
|
|
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
|
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
|
|
|
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
|
|
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
|
|
| BATL_PP_RW \
|
|
| BATL_CACHEINHIBIT \
|
|
| BATL_GUARDEDSTORAGE)
|
|
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
|
|
| BATU_BL_4M \
|
|
| BATU_VS \
|
|
| BATU_VP)
|
|
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
|
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
|
|
|
/* BCSR: cache-inhibit and guarded */
|
|
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
|
|
| BATL_PP_RW \
|
|
| BATL_CACHEINHIBIT \
|
|
| BATL_GUARDEDSTORAGE)
|
|
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
|
|
| BATU_BL_128K \
|
|
| BATU_VS \
|
|
| BATU_VP)
|
|
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
|
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
|
|
|
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
|
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
|
|
| BATL_PP_RW \
|
|
| BATL_MEMCOHERENCE)
|
|
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
|
|
| BATU_BL_32M \
|
|
| BATU_VS \
|
|
| BATU_VP)
|
|
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
|
|
| BATL_PP_RW \
|
|
| BATL_CACHEINHIBIT \
|
|
| BATL_GUARDEDSTORAGE)
|
|
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
|
|
|
/* DDR/LBC SDRAM next 256M: cacheable */
|
|
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \
|
|
| BATL_PP_RW \
|
|
| BATL_MEMCOHERENCE)
|
|
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \
|
|
| BATU_BL_256M \
|
|
| BATU_VS \
|
|
| BATU_VP)
|
|
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
|
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
|
|
|
/* Stack in dcache: cacheable, no memory coherence */
|
|
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
|
|
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
|
|
| BATU_BL_128K \
|
|
| BATU_VS \
|
|
| BATU_VP)
|
|
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
|
|
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
|
|
|
#ifdef CONFIG_PCI
|
|
/* PCI MEM space: cacheable */
|
|
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
|
|
| BATL_PP_RW \
|
|
| BATL_MEMCOHERENCE)
|
|
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
|
|
| BATU_BL_256M \
|
|
| BATU_VS \
|
|
| BATU_VP)
|
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
|
/* PCI MMIO space: cache-inhibit and guarded */
|
|
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
|
|
| BATL_PP_RW \
|
|
| BATL_CACHEINHIBIT \
|
|
| BATL_GUARDEDSTORAGE)
|
|
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
|
|
| BATU_BL_256M \
|
|
| BATU_VS \
|
|
| BATU_VP)
|
|
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
|
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
|
#else
|
|
#define CONFIG_SYS_IBAT6L (0)
|
|
#define CONFIG_SYS_IBAT6U (0)
|
|
#define CONFIG_SYS_IBAT7L (0)
|
|
#define CONFIG_SYS_IBAT7U (0)
|
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
|
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
|
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
|
#endif
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
|
#endif
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
|
|
#define CONFIG_ENV_OVERWRITE
|
|
|
|
#if defined(CONFIG_UEC_ETH)
|
|
#define CONFIG_HAS_ETH0
|
|
#define CONFIG_HAS_ETH1
|
|
#endif
|
|
|
|
#define CONFIG_BAUDRATE 115200
|
|
|
|
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
|
|
|
|
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"netdev=eth0\0" \
|
|
"consoledev=ttyS0\0" \
|
|
"ramdiskaddr=1000000\0" \
|
|
"ramdiskfile=ramfs.83xx\0" \
|
|
"fdtaddr=780000\0" \
|
|
"fdtfile=mpc836x_mds.dtb\0" \
|
|
""
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
|
|
"$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr - $fdtaddr"
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
|
|
|
|
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
|
|
|
#endif /* __CONFIG_H */
|
|
|