upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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494 lines
18 KiB
494 lines
18 KiB
/**
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* @file IxOsalMemAccess.h
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*
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* @brief Header file for memory access
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*
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* @par
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* @version $Revision: 1.0 $
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#ifndef IxOsalMemAccess_H
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#define IxOsalMemAccess_H
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/* Global BE switch
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*
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* Should be set only in BE mode and only if the component uses I/O memory.
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*/
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#if defined (__BIG_ENDIAN)
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#define IX_OSAL_BE_MAPPING
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#endif /* Global switch */
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/* By default only static memory maps in use;
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define IX_OSAL_DYNAMIC_MEMORY_MAP per component if dynamic maps are
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used instead in that component */
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#define IX_OSAL_STATIC_MEMORY_MAP
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/*
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* SDRAM coherency mode
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* Must be defined to BE, LE_DATA_COHERENT or LE_ADDRESS_COHERENT.
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* The mode changes depending on OS
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*/
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#if defined (IX_OSAL_LINUX_BE) || defined (IX_OSAL_VXWORKS_BE)
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#define IX_SDRAM_BE
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#elif defined (IX_OSAL_VXWORKS_LE)
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#define IX_SDRAM_LE_DATA_COHERENT
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#elif defined (IX_OSAL_LINUX_LE)
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#define IX_SDRAM_LE_DATA_COHERENT
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#elif defined (IX_OSAL_WINCE_LE)
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#define IX_SDRAM_LE_DATA_COHERENT
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#elif defined (IX_OSAL_EBOOT_LE)
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#define IX_SDRAM_LE_ADDRESS_COHERENT
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#endif
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/**************************************
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* Retrieve current component mapping *
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**************************************/
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/*
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* Only use customized mapping for LE.
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*
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*/
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#if defined (IX_OSAL_VXWORKS_LE) || defined (IX_OSAL_LINUX_LE) || defined (IX_OSAL_WINCE_LE) || defined (IX_OSAL_EBOOT_LE)
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#include "IxOsalOsIxp400CustomizedMapping.h"
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#endif
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/*******************************************************************
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* Turn off IX_STATIC_MEMORY map for components using dynamic maps *
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*******************************************************************/
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#ifdef IX_OSAL_DYNAMIC_MEMORY_MAP
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#undef IX_OSAL_STATIC_MEMORY_MAP
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#endif
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/************************************************************
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* Turn off BE access for components using LE or no mapping *
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************************************************************/
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#if ( defined (IX_OSAL_LE_AC_MAPPING) || defined (IX_OSAL_LE_DC_MAPPING) || defined (IX_OSAL_NO_MAPPING) )
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#undef IX_OSAL_BE_MAPPING
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#endif
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/*****************
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* Safety checks *
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*****************/
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/* Default to no_mapping */
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#if !defined (IX_OSAL_BE_MAPPING) && !defined (IX_OSAL_LE_AC_MAPPING) && !defined (IX_OSAL_LE_DC_MAPPING) && !defined (IX_OSAL_NO_MAPPING)
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#define IX_OSAL_NO_MAPPING
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#endif /* check at least one mapping */
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/* No more than one mapping can be defined for a component */
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#if (defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING)) \
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||(defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_LE_DC_MAPPING)) \
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||(defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_NO_MAPPING)) \
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||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_NO_MAPPING)) \
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||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING)) \
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||(defined (IX_OSAL_LE_AC_MAPPING) && defined (IX_OSAL_NO_MAPPING))
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#ifdef IX_OSAL_BE_MAPPING
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#warning IX_OSAL_BE_MAPPING is defined
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#endif
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#ifdef IX_OSAL_LE_AC_MAPPING
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#warning IX_OSAL_LE_AC_MAPPING is defined
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#endif
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#ifdef IX_OSAL_LE_DC_MAPPING
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#warning IX_OSAL_LE_DC_MAPPING is defined
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#endif
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#ifdef IX_OSAL_NO_MAPPING
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#warning IX_OSAL_NO_MAPPING is defined
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#endif
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#error More than one I/O mapping is defined, please check your component mapping
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#endif /* check at most one mapping */
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/* Now set IX_OSAL_COMPONENT_MAPPING */
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#ifdef IX_OSAL_BE_MAPPING
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#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_BE
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#endif
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#ifdef IX_OSAL_LE_AC_MAPPING
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#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_AC
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#endif
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#ifdef IX_OSAL_LE_DC_MAPPING
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#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_DC
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#endif
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#ifdef IX_OSAL_NO_MAPPING
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#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE
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#endif
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/* SDRAM coherency should be defined */
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#if !defined (IX_SDRAM_BE) && !defined (IX_SDRAM_LE_DATA_COHERENT) && !defined (IX_SDRAM_LE_ADDRESS_COHERENT)
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#error SDRAM coherency must be defined
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#endif /* SDRAM coherency must be defined */
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/* SDRAM coherency cannot be defined in several ways */
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#if (defined (IX_SDRAM_BE) && (defined (IX_SDRAM_LE_DATA_COHERENT) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
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|| (defined (IX_SDRAM_LE_DATA_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
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|| (defined (IX_SDRAM_LE_ADDRESS_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_DATA_COHERENT)))
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#error SDRAM coherency cannot be defined in more than one way
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#endif /* SDRAM coherency must be defined exactly once */
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/*********************
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* Read/write macros *
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*********************/
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/* WARNING - except for addition of special cookie read/write macros (see below)
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these macros are NOT user serviceable. Please do not modify */
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#define IX_OSAL_READ_LONG_RAW(wAddr) (*(wAddr))
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#define IX_OSAL_READ_SHORT_RAW(sAddr) (*(sAddr))
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#define IX_OSAL_READ_BYTE_RAW(bAddr) (*(bAddr))
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#define IX_OSAL_WRITE_LONG_RAW(wAddr, wData) (*(wAddr) = (wData))
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#define IX_OSAL_WRITE_SHORT_RAW(sAddr,sData) (*(sAddr) = (sData))
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#define IX_OSAL_WRITE_BYTE_RAW(bAddr, bData) (*(bAddr) = (bData))
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#ifdef __linux
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/* Linux - specific cookie reads/writes.
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Redefine per OS if dynamic memory maps are used
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and I/O memory is accessed via functions instead of raw pointer access. */
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#define IX_OSAL_READ_LONG_COOKIE(wCookie) (readl((UINT32) (wCookie) ))
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#define IX_OSAL_READ_SHORT_COOKIE(sCookie) (readw((UINT32) (sCookie) ))
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#define IX_OSAL_READ_BYTE_COOKIE(bCookie) (readb((UINT32) (bCookie) ))
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#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData) (writel(wData, (UINT32) (wCookie) ))
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#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData) (writew(sData, (UINT32) (sCookie) ))
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#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData) (writeb(bData, (UINT32) (bCookie) ))
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#endif /* linux */
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#ifdef __wince
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/* WinCE - specific cookie reads/writes. */
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static __inline__ UINT32
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ixOsalWinCEReadLCookie (volatile UINT32 * lCookie)
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{
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return *lCookie;
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}
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static __inline__ UINT16
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ixOsalWinCEReadWCookie (volatile UINT16 * wCookie)
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{
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#if 0
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UINT32 auxVal = *((volatile UINT32 *) wCookie);
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if ((unsigned) wCookie & 3)
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return (UINT16) (auxVal >> 16);
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else
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return (UINT16) (auxVal & 0xffff);
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#else
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return *wCookie;
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#endif
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}
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static __inline__ UINT8
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ixOsalWinCEReadBCookie (volatile UINT8 * bCookie)
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{
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#if 0
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UINT32 auxVal = *((volatile UINT32 *) bCookie);
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return (UINT8) ((auxVal >> (3 - (((unsigned) bCookie & 3) << 3)) & 0xff));
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#else
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return *bCookie;
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#endif
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}
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static __inline__ void
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ixOsalWinCEWriteLCookie (volatile UINT32 * lCookie, UINT32 lVal)
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{
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*lCookie = lVal;
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}
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static __inline__ void
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ixOsalWinCEWriteWCookie (volatile UINT16 * wCookie, UINT16 wVal)
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{
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#if 0
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volatile UINT32 *auxCookie =
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(volatile UINT32 *) ((unsigned) wCookie & ~3);
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if ((unsigned) wCookie & 3)
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{
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*auxCookie &= 0xffff;
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*auxCookie |= (UINT32) wVal << 16;
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}
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else
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{
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*auxCookie &= ~0xffff;
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*auxCookie |= (UINT32) wVal & 0xffff;
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}
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#else
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*wCookie = wVal;
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#endif
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}
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static __inline__ void
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ixOsalWinCEWriteBCookie (volatile UINT8 * bCookie, UINT8 bVal)
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{
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#if 0
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volatile UINT32 *auxCookie =
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(volatile UINT32 *) ((unsigned) bCookie & ~3);
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*auxCookie &= 0xff << (3 - (((unsigned) bCookie & 3) << 3));
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*auxCookie |= (UINT32) bVal << (3 - (((unsigned) bCookie & 3) << 3));
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#else
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*bCookie = bVal;
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#endif
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}
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#define IX_OSAL_READ_LONG_COOKIE(wCookie) (ixOsalWinCEReadLCookie(wCookie))
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#define IX_OSAL_READ_SHORT_COOKIE(sCookie) (ixOsalWinCEReadWCookie(sCookie))
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#define IX_OSAL_READ_BYTE_COOKIE(bCookie) (ixOsalWinCEReadBCookie(bCookie))
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#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData) (ixOsalWinCEWriteLCookie(wCookie, wData))
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#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData) (ixOsalWinCEWriteWCookie(sCookie, sData))
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#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData) (ixOsalWinCEWriteBCookie(bCookie, bData))
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#endif /* wince */
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#if defined (__vxworks) || (defined (__linux) && defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
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(defined (__wince) && defined (IX_OSAL_STATIC_MEMORY_MAP))
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#define IX_OSAL_READ_LONG_IO(wAddr) IX_OSAL_READ_LONG_RAW(wAddr)
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#define IX_OSAL_READ_SHORT_IO(sAddr) IX_OSAL_READ_SHORT_RAW(sAddr)
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#define IX_OSAL_READ_BYTE_IO(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr)
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#define IX_OSAL_WRITE_LONG_IO(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
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#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
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#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
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#elif (defined (__linux) && !defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
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(defined (__wince) && !defined (IX_OSAL_STATIC_MEMORY_MAP))
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#ifndef __wince
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#include <asm/io.h>
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#endif /* ndef __wince */
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#define IX_OSAL_READ_LONG_IO(wAddr) IX_OSAL_READ_LONG_COOKIE(wAddr)
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#define IX_OSAL_READ_SHORT_IO(sAddr) IX_OSAL_READ_SHORT_COOKIE(sAddr)
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#define IX_OSAL_READ_BYTE_IO(bAddr) IX_OSAL_READ_BYTE_COOKIE(bAddr)
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#define IX_OSAL_WRITE_LONG_IO(wAddr, wData) IX_OSAL_WRITE_LONG_COOKIE(wAddr, wData)
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#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData) IX_OSAL_WRITE_SHORT_COOKIE(sAddr, sData)
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#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData) IX_OSAL_WRITE_BYTE_COOKIE(bAddr, bData)
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#endif
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/* Define BE macros */
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#define IX_OSAL_READ_LONG_BE(wAddr) IX_OSAL_BE_BUSTOXSL(IX_OSAL_READ_LONG_IO((volatile UINT32 *) (wAddr) ))
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#define IX_OSAL_READ_SHORT_BE(sAddr) IX_OSAL_BE_BUSTOXSS(IX_OSAL_READ_SHORT_IO((volatile UINT16 *) (sAddr) ))
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#define IX_OSAL_READ_BYTE_BE(bAddr) IX_OSAL_BE_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
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#define IX_OSAL_WRITE_LONG_BE(wAddr, wData) IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) (wAddr), IX_OSAL_BE_XSTOBUSL((UINT32) (wData) ))
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#define IX_OSAL_WRITE_SHORT_BE(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) (sAddr), IX_OSAL_BE_XSTOBUSS((UINT16) (sData) ))
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#define IX_OSAL_WRITE_BYTE_BE(bAddr, bData) IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_BE_XSTOBUSB((UINT8) (bData) ))
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/* Define LE AC macros */
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#define IX_OSAL_READ_LONG_LE_AC(wAddr) IX_OSAL_READ_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_BUSTOXSL((UINT32) (wAddr) ))
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#define IX_OSAL_READ_SHORT_LE_AC(sAddr) IX_OSAL_READ_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_BUSTOXSS((UINT32) (sAddr) ))
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#define IX_OSAL_READ_BYTE_LE_AC(bAddr) IX_OSAL_READ_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_BUSTOXSB((UINT32) (bAddr) ))
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#define IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData) IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_XSTOBUSL((UINT32) (wAddr) ), (UINT32) (wData))
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#define IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_XSTOBUSS((UINT32) (sAddr) ), (UINT16) (sData))
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#define IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData) IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_XSTOBUSB((UINT32) (bAddr) ), (UINT8) (bData))
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/* Inline functions are required here to avoid reading the same I/O location 2 or 4 times for the byte swap */
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static __inline__ UINT32
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ixOsalDataCoherentLongReadSwap (volatile UINT32 * wAddr)
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{
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UINT32 wData = IX_OSAL_READ_LONG_IO (wAddr);
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return IX_OSAL_LE_DC_BUSTOXSL (wData);
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}
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static __inline__ UINT16
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ixOsalDataCoherentShortReadSwap (volatile UINT16 * sAddr)
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{
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UINT16 sData = IX_OSAL_READ_SHORT_IO (sAddr);
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return IX_OSAL_LE_DC_BUSTOXSS (sData);
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}
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static __inline__ void
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ixOsalDataCoherentLongWriteSwap (volatile UINT32 * wAddr, UINT32 wData)
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{
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wData = IX_OSAL_LE_DC_XSTOBUSL (wData);
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IX_OSAL_WRITE_LONG_IO (wAddr, wData);
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}
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static __inline__ void
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ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
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{
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sData = IX_OSAL_LE_DC_XSTOBUSS (sData);
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IX_OSAL_WRITE_SHORT_IO (sAddr, sData);
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}
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/* Define LE DC macros */
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#define IX_OSAL_READ_LONG_LE_DC(wAddr) ixOsalDataCoherentLongReadSwap((volatile UINT32 *) (wAddr) )
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#define IX_OSAL_READ_SHORT_LE_DC(sAddr) ixOsalDataCoherentShortReadSwap((volatile UINT16 *) (sAddr) )
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#define IX_OSAL_READ_BYTE_LE_DC(bAddr) IX_OSAL_LE_DC_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
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#define IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData) ixOsalDataCoherentLongWriteSwap((volatile UINT32 *) (wAddr), (UINT32) (wData))
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#define IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData) ixOsalDataCoherentShortWriteSwap((volatile UINT16 *) (sAddr), (UINT16) (sData))
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#define IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData) IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_LE_DC_XSTOBUSB((UINT8) (bData)))
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#if defined (IX_OSAL_BE_MAPPING)
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#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_BE(wAddr)
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#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_BE(sAddr)
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#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_BE(bAddr)
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#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_BE(wAddr, wData)
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#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_BE(sAddr, sData)
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#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_BE(bAddr, bData)
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#elif defined (IX_OSAL_LE_AC_MAPPING)
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#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_AC(wAddr)
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#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_AC(sAddr)
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#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_AC(bAddr)
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#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)
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#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData)
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#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)
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#elif defined (IX_OSAL_LE_DC_MAPPING)
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#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_DC(wAddr)
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#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_DC(sAddr)
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#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_DC(bAddr)
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#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)
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#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData)
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#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)
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#endif /* End of BE and LE coherency mode switch */
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/* Reads/writes to and from memory shared with NPEs - depends on the SDRAM coherency */
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#if defined (IX_SDRAM_BE)
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#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_READ_LONG_RAW(wAddr)
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#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_READ_SHORT_RAW(sAddr)
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#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr)
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#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
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#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
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#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
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#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) (wData)
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#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) (sData)
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#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData) (bData)
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#elif defined (IX_SDRAM_LE_ADDRESS_COHERENT)
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#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_READ_LONG_RAW(wAddr)
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#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_READ_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr))
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#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr))
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#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
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#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr), sData)
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#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr), bData)
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#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) (wData)
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#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) (sData)
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#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData) (bData)
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#elif defined (IX_SDRAM_LE_DATA_COHERENT)
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#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_SWAP_LONG(IX_OSAL_READ_LONG_RAW(wAddr))
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#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_SWAP_SHORT(IX_OSAL_READ_SHORT_RAW(sAddr))
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#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr)
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#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, IX_OSAL_SWAP_LONG(wData))
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#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, IX_OSAL_SWAP_SHORT(sData))
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#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
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#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) IX_OSAL_SWAP_LONG(wData)
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#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) IX_OSAL_SWAP_SHORT(sData)
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#endif
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#define IX_OSAL_COPY_BE_SHARED_LONG_ARRAY(wDestAddr, wSrcAddr, wCount) \
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{ \
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UINT32 i; \
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\
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for ( i = 0 ; i < wCount ; i++ ) \
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{ \
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* (((UINT32 *) wDestAddr) + i) = IX_OSAL_READ_BE_SHARED_LONG(((UINT32 *) wSrcAddr) + i); \
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}; \
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};
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#endif /* IxOsalMemAccess_H */
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