upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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246 lines
6.1 KiB
246 lines
6.1 KiB
/*
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* Freescale i.MX28 I2C Driver
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Partly based on Linux kernel i2c-mxs.c driver:
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* Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
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*
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* Which was based on a (non-working) driver which was:
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#define MXS_I2C_MAX_TIMEOUT 1000000
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void mxs_i2c_reset(void)
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{
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struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
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int ret;
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ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
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if (ret) {
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debug("MXS I2C: Block reset timeout\n");
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return;
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}
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writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
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I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
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I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
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&i2c_regs->hw_i2c_ctrl1_clr);
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writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
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}
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void mxs_i2c_setup_read(uint8_t chip, int len)
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{
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struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
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writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
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I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
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(1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
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&i2c_regs->hw_i2c_queuecmd);
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writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);
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writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
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(len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
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I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
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writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
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}
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void mxs_i2c_write(uchar chip, uint addr, int alen,
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uchar *buf, int blen, int stop)
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{
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struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
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uint32_t data;
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int i, remain, off;
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if ((alen > 4) || (alen == 0)) {
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debug("MXS I2C: Invalid address length\n");
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return;
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}
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if (stop)
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stop = I2C_QUEUECMD_POST_SEND_STOP;
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writel(I2C_QUEUECMD_PRE_SEND_START |
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I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
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((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
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&i2c_regs->hw_i2c_queuecmd);
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data = (chip << 1) << 24;
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for (i = 0; i < alen; i++) {
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data >>= 8;
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data |= ((char *)&addr)[alen - i - 1] << 24;
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if ((i & 3) == 2)
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writel(data, &i2c_regs->hw_i2c_data);
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}
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off = i;
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for (; i < off + blen; i++) {
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data >>= 8;
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data |= buf[i - off] << 24;
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if ((i & 3) == 2)
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writel(data, &i2c_regs->hw_i2c_data);
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}
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remain = 24 - ((i & 3) * 8);
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if (remain)
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writel(data >> remain, &i2c_regs->hw_i2c_data);
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writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
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}
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int mxs_i2c_wait_for_ack(void)
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{
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struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
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uint32_t tmp;
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int timeout = MXS_I2C_MAX_TIMEOUT;
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for (;;) {
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tmp = readl(&i2c_regs->hw_i2c_ctrl1);
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if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
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debug("MXS I2C: No slave ACK\n");
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goto err;
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}
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if (tmp & (
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I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
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I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
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debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
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goto err;
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}
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if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
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break;
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if (!timeout--) {
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debug("MXS I2C: Operation timed out\n");
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goto err;
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}
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udelay(1);
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}
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return 0;
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err:
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mxs_i2c_reset();
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return 1;
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}
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
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uint32_t tmp = 0;
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int ret;
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int i;
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mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
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ret = mxs_i2c_wait_for_ack();
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if (ret) {
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debug("MXS I2C: Failed writing address\n");
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return ret;
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}
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mxs_i2c_setup_read(chip, len);
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ret = mxs_i2c_wait_for_ack();
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if (ret) {
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debug("MXS I2C: Failed reading address\n");
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return ret;
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}
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for (i = 0; i < len; i++) {
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if (!(i & 3)) {
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while (readl(&i2c_regs->hw_i2c_queuestat) &
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I2C_QUEUESTAT_RD_QUEUE_EMPTY)
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;
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tmp = readl(&i2c_regs->hw_i2c_queuedata);
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}
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buffer[i] = tmp & 0xff;
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tmp >>= 8;
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}
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return 0;
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}
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int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int ret;
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mxs_i2c_write(chip, addr, alen, buffer, len, 1);
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ret = mxs_i2c_wait_for_ack();
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if (ret)
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debug("MXS I2C: Failed writing address\n");
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return ret;
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}
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int i2c_probe(uchar chip)
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{
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int ret;
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mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
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ret = mxs_i2c_wait_for_ack();
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mxs_i2c_reset();
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return ret;
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}
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void i2c_init(int speed, int slaveadd)
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{
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struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
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mxs_i2c_reset();
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switch (speed) {
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case 100000:
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writel((0x0078 << I2C_TIMING0_HIGH_COUNT_OFFSET) |
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(0x0030 << I2C_TIMING0_RCV_COUNT_OFFSET),
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&i2c_regs->hw_i2c_timing0);
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writel((0x0080 << I2C_TIMING1_LOW_COUNT_OFFSET) |
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(0x0030 << I2C_TIMING1_XMIT_COUNT_OFFSET),
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&i2c_regs->hw_i2c_timing1);
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break;
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case 400000:
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writel((0x000f << I2C_TIMING0_HIGH_COUNT_OFFSET) |
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(0x0007 << I2C_TIMING0_RCV_COUNT_OFFSET),
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&i2c_regs->hw_i2c_timing0);
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writel((0x001f << I2C_TIMING1_LOW_COUNT_OFFSET) |
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(0x000f << I2C_TIMING1_XMIT_COUNT_OFFSET),
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&i2c_regs->hw_i2c_timing1);
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break;
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default:
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printf("MXS I2C: Invalid speed selected (%d Hz)\n", speed);
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return;
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}
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writel((0x0015 << I2C_TIMING2_BUS_FREE_OFFSET) |
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(0x000d << I2C_TIMING2_LEADIN_COUNT_OFFSET),
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&i2c_regs->hw_i2c_timing2);
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return;
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}
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