upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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408 lines
12 KiB
408 lines
12 KiB
/*
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* (C) Copyright 2008-2009
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* BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
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* Jens Scharsig <esw@bus-elektronik.de>
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*
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* Configuation settings for the EB+CPUx9K2 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _CONFIG_EB_CPUx9K2_H_
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#define _CONFIG_EB_CPUx9K2_H_
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/*--------------------------------------------------------------------------*/
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#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
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#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
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#define CONFIG_EB_CPUX9K2 1 /* on an EP+CPUX9K2 Board */
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#define USE_920T_MMU 1
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#define CONFIG_VERSION_VARIABLE 1
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#define CONFIG_IDENT_STRING " on EB+CPUx9K2"
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#include <asm/arch/hardware.h> /* needed for port definitions */
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#define CONFIG_MISC_INIT_R
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/*--------------------------------------------------------------------------*/
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
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#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
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#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
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#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
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#define CONFIG_BOOT_RETRY_TIME 30
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_STACKSIZE (32*1024) /* regular stack */
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/*
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* ARM asynchronous clock
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*/
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#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */
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#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
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#define AT91_SLOW_CLOCK 32768 /* slow clock */
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#define CONFIG_CMDLINE_TAG 1
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
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/* flash */
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#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
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#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
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/* clocks */
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#define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */
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#define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */
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#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 520*1024)
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#define CONFIG_SYS_GBL_DATA_SIZE 128
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/*
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* sdram
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
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CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
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CONFIG_SYS_MALLOC_LEN)
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#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
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#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
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#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
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#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
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#define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */
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#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
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#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
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#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
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#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
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#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
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#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
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#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
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#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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/*
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* Command line configuration
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BMP
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_PING
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#define CONFIG_I2C_CMD_NO_FLAT
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#define CONFIG_I2C_CMD_TREE
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#define CONFIG_SYS_LONGHELP
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/*
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* Filesystems
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*/
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#define CONFIG_JFFS2_NAND 1
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#ifndef CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_DEV "nand0"
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#define CONFIG_JFFS2_PART_OFFSET 0
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#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
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#else
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#define MTDIDS_DEFAULT "nor0=0,nand0=1"
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#define MTDPARTS_DEFAULT "mtdparts=" \
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"0:" \
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"384k(U-Boot)," \
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"128k(Env)," \
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"128k(Splash)," \
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"4M(Kernel)," \
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"-(FS)" \
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";" \
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"1:" \
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"-(jffs2)"
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#endif /* CONFIG_JFFS2_CMDLINE */
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/*
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* Hardware drivers
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*/
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/*
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* UART/CONSOLE
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*/
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_AT91RM9200_USART
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#define CONFIG_DBGU /* define DBGU as console */
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/*
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* network
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*/
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#define CONFIG_NET_MULTI 1
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_RESET_PHY_R 1
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#define CONFIG_DRIVER_AT91EMAC 1
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#define CONFIG_DRIVER_AT91EMAC_QUIET 1
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#define CONFIG_SYS_RX_ETH_BUFFER 8
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#define CONFIG_MII 1
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* I2C-Bus
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*/
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#define CONFIG_SYS_I2C_SPEED 50000
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#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
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#ifndef CONFIG_HARD_I2C
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#define CONFIG_SOFT_I2C
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/* Software I2C driver configuration */
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#define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */
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#define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */
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#define CONFIG_SYS_I2C_INIT_BOARD
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#define I2C_INIT i2c_init_board();
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#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
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#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
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#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
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#define I2C_SDA(bit) \
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if (bit) \
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writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
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else \
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writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
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#define I2C_SCL(bit) \
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if (bit) \
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writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
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else \
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writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
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#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
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#endif /* CONFIG_HARD_I2C */
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/* I2C-RTC */
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#ifdef CONFIG_CMD_DATE
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#define CONFIG_RTC_DS1338
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#endif
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/* EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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/* FLASH organization */
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/* NOR-FLASH */
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define PHYS_FLASH_1 0x10000000
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#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_PROTECTION 1
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#define CONFIG_SYS_FLASH_ERASE_TOUT 6000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 2000
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/* NAND */
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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#define CONFIG_SYS_64BIT_VSPRINTF 1
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/* Status LED's */
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#define CONFIG_STATUS_LED 1
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#define CONFIG_BOARD_SPECIFIC_LED 1
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#define STATUS_LED_BOOT 1
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#define STATUS_LED_ACTIVE 0
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#define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */
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#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
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#define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */
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#define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */
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#define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */
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#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4)
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#define CONFIG_VIDEO 1
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/* Options */
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#ifdef CONFIG_VIDEO
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#define CONFIG_VIDEO_VCXK 1
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#define CONFIG_SPLASH_SCREEN 1
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#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4
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#define CONFIG_SYS_VCXK_BASE 0x30000000
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#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3)
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#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob
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#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr
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#define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5)
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#define CONFIG_SYS_VCXK_ENABLE_PORT piob
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#define CONFIG_SYS_VCXK_ENABLE_DDR oer
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#define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2)
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#define CONFIG_SYS_VCXK_REQUEST_PORT piob
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#define CONFIG_SYS_VCXK_REQUEST_DDR oer
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#define CONFIG_SYS_VCXK_INVERT_PIN (1<<4)
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#define CONFIG_SYS_VCXK_INVERT_PORT piob
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#define CONFIG_SYS_VCXK_INVERT_DDR oer
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#define CONFIG_SYS_VCXK_RESET_PIN (1<<6)
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#define CONFIG_SYS_VCXK_RESET_PORT piob
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#define CONFIG_SYS_VCXK_RESET_DDR oer
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#endif /* CONFIG_VIDEO */
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/* Environment */
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
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#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTCOMMAND "run nfsboot"
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#define CONFIG_NFSBOOTCOMMAND \
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"dhcp $(copy_addr) uImage_cpux9k2;" \
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"run bootargsdefaults;" \
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"set bootargs $(bootargs) boot=nfs " \
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";echo $(bootargs)" \
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";bootm"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"displaywidth=256\0" \
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"displayheight=512\0" \
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"displaybsteps=1023\0" \
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"ubootaddr=10000000\0" \
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"splashimage=10080000\0" \
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"kerneladdr=100A0000\0" \
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"kernelsize=00400000\0" \
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"rootfsaddr=104A0000\0" \
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"copy_addr=21200000\0" \
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"rootfssize=00B60000\0" \
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"bootargsdefaults=set bootargs " \
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"console=ttyS0,115200 " \
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"video=vcxk_fb:xres:${displaywidth}," \
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"yres:${displayheight}," \
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"bres:${displaybsteps} " \
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"mem=62M " \
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"panic=10 " \
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"uboot=\\\"${ver}\\\" " \
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"\0" \
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"update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
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"dhcp $(copy_addr) uImage_cpux9k2;" \
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"erase $(kerneladdr) +$(kernelsize);" \
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"cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
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"protect on $(kerneladdr) +$(kernelsize)" \
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"\0" \
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"update_root=protect off $(rootfsaddr) +$(rootfssize);" \
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"dhcp $(copy_addr) rfs;" \
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"erase $(rootfsaddr) +$(rootfssize);" \
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"cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
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"\0" \
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"update_uboot=protect off 10000000 1005FFFF;" \
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"dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
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"erase 10000000 1005FFFF;" \
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"cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
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"protect on 10000000 1005FFFF;reset\0" \
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"update_splash=protect off $(splashimage) +20000;" \
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"dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
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"erase $(splashimage) +20000;" \
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"cp.b $(fileaddr) 10080000 $(filesize);" \
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"protect on $(splashimage) +20000;reset\0" \
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"emergency=run bootargsdefaults;" \
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"set bootargs $(bootargs) root=initramfs boot=emergency " \
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";bootm $(kerneladdr)\0" \
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"netemergency=run bootargsdefaults;" \
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"dhcp $(copy_addr) uImage_cpux9k2;" \
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"set bootargs $(bootargs) root=initramfs boot=emergency " \
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";bootm $(copy_addr)\0" \
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"norboot=run bootargsdefaults;" \
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"set bootargs $(bootargs) root=initramfs boot=local " \
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";bootm $(kerneladdr)\0" \
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"nandboot=run bootargsdefaults;" \
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"set bootargs $(bootargs) root=initramfs boot=nand " \
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";bootm $(kerneladdr)\0" \
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" "
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/*--------------------------------------------------------------------------*/
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#endif
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/* EOF */
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