upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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497 lines
13 KiB
497 lines
13 KiB
/**
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* @file IxEthMii.c
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*
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* @author Intel Corporation
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* @date
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*
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* @brief MII control functions
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*
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* Design Notes:
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#include "IxOsal.h"
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#include "IxEthAcc.h"
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#include "IxEthMii_p.h"
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#ifdef __wince
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#include "IxOsPrintf.h"
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#endif
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/* Array to store the phy IDs of the discovered phys */
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PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR];
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/*********************************************************
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*
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* Scan for PHYs on the MII bus. This function returns
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* an array of booleans, one for each PHY address.
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* If a PHY is found at a particular address, the
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* corresponding entry in the array is set to true.
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*
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*/
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PUBLIC IX_STATUS
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ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
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{
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UINT32 i;
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UINT16 regval, regvalId1, regvalId2;
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/*Search for PHYs on the MII*/
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/*Search for existant phys on the MDIO bus*/
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if ((phyPresent == NULL) ||
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(maxPhyCount > IXP425_ETH_ACC_MII_MAX_ADDR))
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{
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return IX_FAIL;
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}
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/* fill the array */
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for(i=0;
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i<IXP425_ETH_ACC_MII_MAX_ADDR;
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i++)
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{
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phyPresent[i] = false;
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}
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/* iterate through the PHY addresses */
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for(i=0;
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maxPhyCount > 0 && i<IXP425_ETH_ACC_MII_MAX_ADDR;
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i++)
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{
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ixEthMiiPhyId[i] = IX_ETH_MII_INVALID_PHY_ID;
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if(ixEthAccMiiReadRtn(i,
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IX_ETH_MII_CTRL_REG,
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®val) == IX_ETH_ACC_SUCCESS)
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{
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if((regval & 0xffff) != 0xffff)
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{
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maxPhyCount--;
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/*Need to read the register twice here to flush PHY*/
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ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID1_REG, ®valId1);
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ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID1_REG, ®valId1);
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ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID2_REG, ®valId2);
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ixEthMiiPhyId[i] = (regvalId1 << IX_ETH_MII_REG_SHL) | regvalId2;
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if ((ixEthMiiPhyId[i] == IX_ETH_MII_KS8995_PHY_ID)
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|| (ixEthMiiPhyId[i] == IX_ETH_MII_LXT971_PHY_ID)
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|| (ixEthMiiPhyId[i] == IX_ETH_MII_LXT972_PHY_ID)
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|| (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973_PHY_ID)
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|| (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973A3_PHY_ID)
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|| (ixEthMiiPhyId[i] == IX_ETH_MII_LXT9785_PHY_ID)
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)
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{
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/* supported phy */
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phyPresent[i] = true;
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} /* end of if(ixEthMiiPhyId) */
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else
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{
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if (ixEthMiiPhyId[i] != IX_ETH_MII_INVALID_PHY_ID)
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{
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/* unsupported phy */
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ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
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IX_OSAL_LOG_DEV_STDOUT,
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"ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n",
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ixEthMiiPhyId[i], 2, 3, 4, 5, 6);
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ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID;
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phyPresent[i] = true;
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}
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}
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}
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}
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}
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return IX_SUCCESS;
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}
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/************************************************************
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*
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* Configure the PHY at the specified address
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*
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*/
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PUBLIC IX_STATUS
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ixEthMiiPhyConfig(UINT32 phyAddr,
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BOOL speed100,
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BOOL fullDuplex,
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BOOL autonegotiate)
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{
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UINT16 regval=0;
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/* parameter check */
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if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
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(ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
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{
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/*
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* set the control register
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*/
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if(autonegotiate)
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{
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regval |= IX_ETH_MII_CR_AUTO_EN | IX_ETH_MII_CR_RESTART;
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}
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else
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{
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if(speed100)
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{
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regval |= IX_ETH_MII_CR_100;
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}
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if(fullDuplex)
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{
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regval |= IX_ETH_MII_CR_FDX;
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}
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} /* end of if-else() */
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if (ixEthAccMiiWriteRtn(phyAddr,
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IX_ETH_MII_CTRL_REG,
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regval) == IX_ETH_ACC_SUCCESS)
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{
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return IX_SUCCESS;
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}
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} /* end of if(phyAddr) */
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return IX_FAIL;
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}
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/******************************************************************
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*
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* Enable the PHY Loopback at the specified address
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*/
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PUBLIC IX_STATUS
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ixEthMiiPhyLoopbackEnable (UINT32 phyAddr)
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{
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UINT16 regval ;
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if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
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(IX_ETH_MII_INVALID_PHY_ID != ixEthMiiPhyId[phyAddr]))
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{
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/* read/write the control register */
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if(ixEthAccMiiReadRtn (phyAddr,
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IX_ETH_MII_CTRL_REG,
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®val)
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== IX_ETH_ACC_SUCCESS)
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{
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if(ixEthAccMiiWriteRtn (phyAddr,
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IX_ETH_MII_CTRL_REG,
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regval | IX_ETH_MII_CR_LOOPBACK)
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== IX_ETH_ACC_SUCCESS)
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{
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return IX_SUCCESS;
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}
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}
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}
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return IX_FAIL;
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}
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/******************************************************************
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*
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* Disable the PHY Loopback at the specified address
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*/
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PUBLIC IX_STATUS
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ixEthMiiPhyLoopbackDisable (UINT32 phyAddr)
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{
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UINT16 regval ;
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if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
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(IX_ETH_MII_INVALID_PHY_ID != ixEthMiiPhyId[phyAddr]))
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{
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/* read/write the control register */
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if(ixEthAccMiiReadRtn (phyAddr,
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IX_ETH_MII_CTRL_REG,
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®val)
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== IX_ETH_ACC_SUCCESS)
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{
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if(ixEthAccMiiWriteRtn (phyAddr,
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IX_ETH_MII_CTRL_REG,
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regval & (~IX_ETH_MII_CR_LOOPBACK))
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== IX_ETH_ACC_SUCCESS)
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{
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return IX_SUCCESS;
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}
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}
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}
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return IX_FAIL;
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}
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/******************************************************************
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*
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* Reset the PHY at the specified address
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*/
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PUBLIC IX_STATUS
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ixEthMiiPhyReset(UINT32 phyAddr)
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{
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UINT32 timeout;
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UINT16 regval;
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if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
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(ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
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{
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if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID) ||
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(ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID) ||
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(ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973_PHY_ID) ||
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(ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973A3_PHY_ID) ||
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(ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
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)
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{
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/* use the control register to reset the phy */
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ixEthAccMiiWriteRtn(phyAddr,
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IX_ETH_MII_CTRL_REG,
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IX_ETH_MII_CR_RESET);
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/* poll until the reset bit is cleared */
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timeout = 0;
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do
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{
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ixOsalSleep (IX_ETH_MII_RESET_POLL_MS);
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/* read the control register and check for timeout */
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ixEthAccMiiReadRtn(phyAddr,
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IX_ETH_MII_CTRL_REG,
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®val);
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if ((regval & IX_ETH_MII_CR_RESET) == 0)
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{
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/* timeout bit is self-cleared */
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break;
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}
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timeout += IX_ETH_MII_RESET_POLL_MS;
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}
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while (timeout < IX_ETH_MII_RESET_DELAY_MS);
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/* check for timeout */
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if (timeout >= IX_ETH_MII_RESET_DELAY_MS)
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{
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ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
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IX_ETH_MII_CR_NORM_EN);
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return IX_FAIL;
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}
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return IX_SUCCESS;
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} /* end of if(ixEthMiiPhyId) */
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else if (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_KS8995_PHY_ID)
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{
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/* reset bit is reserved, just reset the control register */
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ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
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IX_ETH_MII_CR_NORM_EN);
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return IX_SUCCESS;
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}
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else
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{
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/* unknown PHY, set the control register reset bit,
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* wait 2 s. and clear the control register.
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*/
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ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
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IX_ETH_MII_CR_RESET);
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ixOsalSleep (IX_ETH_MII_RESET_DELAY_MS);
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ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
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IX_ETH_MII_CR_NORM_EN);
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return IX_SUCCESS;
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} /* end of if-else(ixEthMiiPhyId) */
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} /* end of if(phyAddr) */
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return IX_FAIL;
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}
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/*****************************************************************
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*
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* Link state query functions
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*/
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PUBLIC IX_STATUS
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ixEthMiiLinkStatus(UINT32 phyAddr,
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BOOL *linkUp,
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BOOL *speed100,
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BOOL *fullDuplex,
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BOOL *autoneg)
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{
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UINT16 ctrlRegval, statRegval, regval, regval4, regval5;
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/* check the parameters */
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if ((linkUp == NULL) ||
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(speed100 == NULL) ||
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(fullDuplex == NULL) ||
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(autoneg == NULL))
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{
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return IX_FAIL;
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}
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*linkUp = false;
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*speed100 = false;
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*fullDuplex = false;
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*autoneg = false;
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if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
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(ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
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{
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if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID) ||
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(ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID) ||
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(ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
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)
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{
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/* --------------------------------------------------*/
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/* Retrieve information from PHY specific register */
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/* --------------------------------------------------*/
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if (ixEthAccMiiReadRtn(phyAddr,
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IX_ETH_MII_STAT2_REG,
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®val) != IX_ETH_ACC_SUCCESS)
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{
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return IX_FAIL;
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}
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*linkUp = ((regval & IX_ETH_MII_SR2_LINK) != 0);
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*speed100 = ((regval & IX_ETH_MII_SR2_100) != 0);
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*fullDuplex = ((regval & IX_ETH_MII_SR2_FD) != 0);
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*autoneg = ((regval & IX_ETH_MII_SR2_AUTO) != 0);
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return IX_SUCCESS;
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} /* end of if(ixEthMiiPhyId) */
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else
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{
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/* ----------------------------------------------------*/
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/* Retrieve information from status and ctrl registers */
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/* ----------------------------------------------------*/
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if (ixEthAccMiiReadRtn(phyAddr,
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IX_ETH_MII_CTRL_REG,
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&ctrlRegval) != IX_ETH_ACC_SUCCESS)
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{
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return IX_FAIL;
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}
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &statRegval);
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*linkUp = ((statRegval & IX_ETH_MII_SR_LINK_STATUS) != 0);
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if (*linkUp)
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{
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*autoneg = ((ctrlRegval & IX_ETH_MII_CR_AUTO_EN) != 0) &&
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((statRegval & IX_ETH_MII_SR_AUTO_SEL) != 0) &&
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((statRegval & IX_ETH_MII_SR_AUTO_NEG) != 0);
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if (*autoneg)
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{
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/* mask the current stat values with the capabilities */
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_ADS_REG, ®val4);
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_PRTN_REG, ®val5);
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/* merge the flags from the 3 registers */
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regval = (statRegval & ((regval4 & regval5) << 6));
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/* initialise from status register values */
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if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0)
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{
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/* 100 Base X full dplx */
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*speed100 = true;
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*fullDuplex = true;
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return IX_SUCCESS;
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}
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if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0)
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{
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/* 100 Base X half dplx */
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*speed100 = true;
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return IX_SUCCESS;
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}
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if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0)
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{
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/* 10 mb full dplx */
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*fullDuplex = true;
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return IX_SUCCESS;
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}
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if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0)
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{
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/* 10 mb half dplx */
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return IX_SUCCESS;
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}
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} /* end of if(autoneg) */
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else
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{
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/* autonegotiate not complete, return setup parameters */
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*speed100 = ((ctrlRegval & IX_ETH_MII_CR_100) != 0);
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*fullDuplex = ((ctrlRegval & IX_ETH_MII_CR_FDX) != 0);
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}
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} /* end of if(linkUp) */
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} /* end of if-else(ixEthMiiPhyId) */
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} /* end of if(phyAddr) */
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else
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{
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return IX_FAIL;
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} /* end of if-else(phyAddr) */
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return IX_SUCCESS;
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}
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/*****************************************************************
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*
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* Link state display functions
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*/
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PUBLIC IX_STATUS
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ixEthMiiPhyShow (UINT32 phyAddr)
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{
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BOOL linkUp, speed100, fullDuplex, autoneg;
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UINT16 cregval;
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UINT16 sregval;
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|
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &sregval);
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_CTRL_REG, &cregval);
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/* get link information */
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if (ixEthMiiLinkStatus(phyAddr,
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&linkUp,
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&speed100,
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&fullDuplex,
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&autoneg) != IX_ETH_ACC_SUCCESS)
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{
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printf("PHY Status unknown\n");
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return IX_FAIL;
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}
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printf("PHY ID [phyAddr]: %8.8x\n",ixEthMiiPhyId[phyAddr]);
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printf( " Status reg: %4.4x\n",sregval);
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printf( " control reg: %4.4x\n",cregval);
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/* display link information */
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printf("PHY Status:\n");
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printf(" Link is %s\n",
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(linkUp ? "Up" : "Down"));
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if((sregval & IX_ETH_MII_SR_REMOTE_FAULT) != 0)
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{
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printf(" Remote fault detected\n");
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}
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printf(" Auto Negotiation %s\n",
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(autoneg ? "Completed" : "Not Completed"));
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printf("PHY Configuration:\n");
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printf(" Speed %sMb/s\n",
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(speed100 ? "100" : "10"));
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printf(" %s Duplex\n",
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(fullDuplex ? "Full" : "Half"));
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printf(" Auto Negotiation %s\n",
|
|
(autoneg ? "Enabled" : "Disabled"));
|
|
return IX_SUCCESS;
|
|
}
|
|
|
|
|